Fix various tool compatibility issues (#4)

* Fix tool compatibility issues

README.md

@@ -165,6 +165,9 @@ If you use FPnew in your work, you can cite us:
 }
 ```
 
+<p>
+</details>
+
 If you use FPnew SDOTP in your work, you can cite us:
 
 <details>

docs/CHANGELOG-PULP.md

@@ -7,6 +7,11 @@ The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/) a
 In this sense, we interpret the "Public API" of a hardware module as its port/parameter list.
 Versions of the IP in the same major relase are "pin-compatible" with each other. Minor relases are permitted to add new parameters as long as their default bindings ensure backwards compatibility.
 
+## [0.1.1] - 2023-05-05
+
+### Fixed
+- Fix various tool compatibility issues
+
 ## [0.1.0] - 2023-05-04
 
 ### Added

src/fpnew_opgroup_block.sv

@@ -25,8 +25,8 @@ module fpnew_opgroup_block #(
   parameter fpnew_pkg::fmt_unit_types_t FmtUnitTypes  = '{default: fpnew_pkg::PARALLEL},
   parameter fpnew_pkg::pipe_config_t    PipeConfig    = fpnew_pkg::BEFORE,
   parameter type                        TagType       = logic,
-  parameter int unsigned                TrueSIMDClass = 0,
-  parameter logic                       CompressedVecCmpResult = 0,
+  parameter logic                       TrueSIMDClass = 1'b0,
+  parameter logic                       CompressedVecCmpResult = 1'b0,
   parameter fpnew_pkg::rsr_impl_t       StochasticRndImplementation = fpnew_pkg::DEFAULT_NO_RSR,
   // Do not change
   localparam int unsigned NUM_FORMATS  = fpnew_pkg::NUM_FP_FORMATS,

src/fpnew_opgroup_fmt_slice.sv

@@ -22,8 +22,8 @@ module fpnew_opgroup_fmt_slice #(
   parameter int unsigned             NumPipeRegs   = 0,
   parameter fpnew_pkg::pipe_config_t PipeConfig    = fpnew_pkg::BEFORE,
   parameter type                     TagType       = logic,
-  parameter int unsigned             TrueSIMDClass = 0,
-  parameter logic                    CompressedVecCmpResult = 0,
+  parameter logic                    TrueSIMDClass = 1'b0,
+  parameter logic                    CompressedVecCmpResult = 1'b0,
   // Do not change
   localparam int unsigned NUM_OPERANDS = fpnew_pkg::num_operands(OpGroup),
   localparam int unsigned NUM_LANES    = fpnew_pkg::num_lanes(Width, FpFormat, EnableVectors),

src/fpnew_opgroup_multifmt_slice.sv

@@ -315,7 +315,7 @@ or on 16b inputs producing 32b outputs");
           .busy_o          ( lane_busy[lane]     )
         );
       end else if (OpGroup == fpnew_pkg::DIVSQRT) begin : lane_instance
-        if (!PulpDivsqrt && LANE_FORMATS[0] && (LANE_FORMATS[1:fpnew_pkg::NUM_FP_FORMATS-1] == '0)) begin : gen_th_32_divsqrt
+        if (!PulpDivsqrt) begin : gen_th_32_divsqrt
           // The T-head-based DivSqrt unit is supported only in FP32-only configurations
           fpnew_divsqrt_th_32 #(
             .NumPipeRegs ( NumPipeRegs          ),
@@ -433,6 +433,7 @@ or on 16b inputs producing 32b outputs");
       assign lane_out_valid[lane] = 1'b0; // unused lane
       assign lane_in_ready[lane]  = 1'b0; // unused lane
       assign lane_aux[lane]       = 1'b0; // unused lane
+      assign lane_masks[lane]     = 1'b1; // unused lane
       assign lane_tags[lane]      = 1'b0; // unused lane
       assign lane_ext_bit[lane]   = 1'b1; // NaN-box unused lane
       assign local_result         = {(LANE_WIDTH){lane_ext_bit[0]}}; // sign-extend/nan box
@@ -571,7 +572,7 @@ or on 16b inputs producing 32b outputs");
     assign fmt_conv_cpk_result = '0;
   end
 
-  if (PulpDivsqrt) begin
+  if (PulpDivsqrt && (OpGroup == fpnew_pkg::DIVSQRT)) begin
     // Synch lanes if there is more than one
     assign simd_synch_rdy  = EnableVectors ? &divsqrt_ready : divsqrt_ready[0];
     assign simd_synch_done = EnableVectors ? &divsqrt_done  : divsqrt_done[0];

src/fpnew_sdotp_multi.sv

@@ -1270,7 +1270,7 @@ module fpnew_sdotp_multi #(
     // Set up some constants
     localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt));
     localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt));
-    localparam int unsigned ALL_EXTRA_BITS = SUPER_DST_MAN_BITS-MAN_BITS+1+DST_PRECISION_BITS+PRECISION_BITS+2+1;
+    localparam int unsigned ALL_EXTRA_BITS = fpnew_pkg::maximum(SUPER_DST_MAN_BITS-MAN_BITS+1+DST_PRECISION_BITS+PRECISION_BITS+2+1, 1);
 
     logic [EXP_BITS-1:0] pre_round_exponent;
     logic [MAN_BITS-1:0] pre_round_mantissa;

src/fpnew_sdotp_multi_wrapper.sv

@@ -28,8 +28,8 @@ module fpnew_sdotp_multi_wrapper #(
   // Do not change
   localparam fpnew_pkg::fmt_logic_t FpSrcFmtConfig = FpFmtConfig[0] ? (FpFmtConfig & 6'b001111) : (FpFmtConfig & 6'b000101),
   localparam fpnew_pkg::fmt_logic_t FpDstFmtConfig = fpnew_pkg::get_dotp_dst_fmts(FpFmtConfig, FpSrcFmtConfig),
-  localparam int                    SRC_WIDTH      = fpnew_pkg::max_fp_width(FpSrcFmtConfig),
-  localparam int                    DST_WIDTH      = 2*fpnew_pkg::max_fp_width(FpSrcFmtConfig), // do not change, current assumption of sdotpex_multi
+  localparam int                    SRC_WIDTH      = fpnew_pkg::maximum(fpnew_pkg::max_fp_width(FpSrcFmtConfig), 1),
+  localparam int                    DST_WIDTH      = fpnew_pkg::maximum(2*fpnew_pkg::max_fp_width(FpSrcFmtConfig), 1), // do not change, current assumption of sdotpex_multi
   localparam int                    OPERAND_WIDTH  = LaneWidth,
   localparam int unsigned           NUM_FORMATS    = fpnew_pkg::NUM_FP_FORMATS
 ) (

src/fpnew_top.sv

@@ -20,9 +20,9 @@ module fpnew_top #(
   // PulpDivSqrt = 0 enables T-head-based DivSqrt unit. Supported only for FP32-only instances of Fpnew
   parameter logic                           PulpDivsqrt    = 1'b1,
   parameter type                            TagType        = logic,
-  parameter int unsigned                    TrueSIMDClass  = 0,
-  parameter int unsigned                    EnableSIMDMask = 0,
-  parameter logic                           CompressedVecCmpResult = 0, // conceived for RV32FD cores
+  parameter logic                           TrueSIMDClass  = 1'b0,
+  parameter logic                           EnableSIMDMask = 1'b0,
+  parameter logic                           CompressedVecCmpResult = 1'b0, // conceived for RV32FD cores
   parameter fpnew_pkg::rsr_impl_t           StochasticRndImplementation = fpnew_pkg::DEFAULT_NO_RSR,
   // Do not change
   localparam int unsigned NumLanes     = fpnew_pkg::max_num_lanes(Features.Width, Features.FpFmtMask, Features.EnableVectors),
@@ -99,7 +99,7 @@ module fpnew_top #(
 
   // Filter out the mask if not used
   MaskType simd_mask;
-  assign simd_mask = simd_mask_i | ~{NumLanes{logic'(EnableSIMDMask)}};
+  assign simd_mask = simd_mask_i | ~{NumLanes{EnableSIMDMask}};
 
   // -------------------------
   // Generate Operation Blocks