[Verification] UART Debugging and Writeback

[viv-eth]

Description

This PR adds UART debugging capabilities in the vip_chimera_soc.sv module by introducing a writeback mechanism and a FIFO for writeback handling in the testbench.

Changes

• Added a new UART writeback mechanism:
  • Introduced a UartWriteBack[5:0] local parameter with the value "UartWB".
  • Implemented a comparison against UartWriteBack in the UART handling logic.
  • When a match is detected, a predefined writeback message ("WB OK") is sent via UART.
• Added a FIFO buffer for UART writeback:
  • Introduced a static FIFO (uart_fifo) to store all received bytes.
  • Enables the testbench to track UART transactions and trigger the writeback message.

Motivation

• This change was made to test the functionality of the UART peripheral in Chimera after implementing its driver and HAL in the chimera-sdk. This is related to PR #11, which is currently pending review.
• The writeback mechanism allows us to verify that the UART driver properly handles received data and responds as expected.
• The FIFO ensures that incoming UART data is stored and processed correctly for triggering writebacks.

Testing

• Simulated the vip_chimera_soc module to verify correct handling of the UART FIFO and writeback message using the tests in the chimera-sdk.
• Confirmed that expected messages are displayed when "UartWB" is received.