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fix issue #224 : add field_tag into address representation #227

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fix issue #224 : add field_tag into address representation #227

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383fbc3
fix_issue_224
DreamWuGit Jun 21, 2022
af72a8e
use 32 bits for index
DreamWuGit Jun 22, 2022
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4 changes: 2 additions & 2 deletions src/zkevm_specs/evm/instruction.py
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Original file line number Diff line number Diff line change
Expand Up @@ -500,9 +500,9 @@ def tx_log_lookup(
RW.Write,
RWTableTag.TxLog,
key1=tx_id,
key2=log_id,
key2=FQ(index + int(field_tag) << 32 + log_id.expr().n << 48),
key3=FQ(field_tag),
key4=FQ(index),
key4=FQ(0),
).value
return value

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8 changes: 4 additions & 4 deletions src/zkevm_specs/evm/typing.py
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Original file line number Diff line number Diff line change
Expand Up @@ -374,9 +374,9 @@ def call_context_write(
def tx_log_write(
self,
tx_id: IntOrFQ,
log_id: IntOrFQ,
log_id: int,
field_tag: TxLogFieldTag,
index: IntOrFQ,
index: int,
value: Union[int, FQ, RLC],
) -> RWDictionary:
if isinstance(value, int):
Expand All @@ -385,9 +385,9 @@ def tx_log_write(
RW.Write,
RWTableTag.TxLog,
key1=FQ(tx_id),
key2=FQ(log_id),
key2=FQ(index + int(field_tag) << 32 + log_id << 48),
key3=FQ(field_tag),
key4=FQ(index),
key4=FQ(0),
value=value,
)

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