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accel/ivpu: Clear specific interrupt status bits on C0
MTL C0 stepping fixed issue related to butrress interrupt status clearing, to clear an interrupt status it is required to write 1 to specific status bit field. This allows to execute read, modify and write routine. Writing 0 will not clear the interrupt and will cause interrupt storm. Fixes: 35b1376 ("accel/ivpu: Introduce a new DRM driver for Intel VPU") Cc: [email protected] # 6.3.x Signed-off-by: Karol Wachowski <[email protected]> Reviewed-by: Jacek Lawrynowicz <[email protected]> Signed-off-by: Stanislaw Gruszka <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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