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Merge pull request #2 from Liaoshihua/rvp-rebase-1
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Support packed simd extension in binutils
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@pz9115
pz9115 authored Jul 26, 2023
2 parents 8bddb52 + 5651d37 commit bd7801d
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Showing 16 changed files with 2,414 additions and 4 deletions.
25 changes: 25 additions & 0 deletions bfd/elfxx-riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1226,6 +1226,9 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvl16384b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32768b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl65536b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zbpbo", ISA_SPEC_CLASS_DRAFT, 0, 9, 11 },
{"zpn", ISA_SPEC_CLASS_DRAFT, 0, 9, 11 },
{"zpsf", ISA_SPEC_CLASS_DRAFT, 0, 9, 11 },
{NULL, 0, 0, 0, 0}
};

Expand Down Expand Up @@ -2392,6 +2395,18 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
return riscv_subset_supports (rps, "h");
case INSN_CLASS_ZPN:
return riscv_subset_supports (rps, "zpn");
case INSN_CLASS_ZPSF:
return riscv_subset_supports (rps, "zpsf");
case INSN_CLASS_ZBPBO:
return riscv_subset_supports (rps, "zbpbo");
case INSN_CLASS_ZBB_OR_ZBPBO:
return (riscv_subset_supports (rps, "zbb")
|| riscv_subset_supports (rps, "zbpbo"));
case INSN_CLASS_ZBKB_OR_ZBPBO:
return (riscv_subset_supports (rps, "zbkb")
|| riscv_subset_supports (rps, "zbpbo"));
default:
rps->error_handler
(_("internal: unreachable INSN_CLASS_*"));
Expand Down Expand Up @@ -2497,6 +2512,16 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("('q' and 'zfh') or 'zhinx");
case INSN_CLASS_H:
return _("h");
case INSN_CLASS_ZPN:
return _("zpn");
case INSN_CLASS_ZPSF:
return _("zpsf");
case INSN_CLASS_ZBPBO:
return _("zbpbo");
case INSN_CLASS_ZBB_OR_ZBPBO:
return _("zbpbo' or `zbb");
case INSN_CLASS_ZBKB_OR_ZBPBO:
return _("zbpbo' or `zbkb");
default:
rps->error_handler
(_("internal: unreachable INSN_CLASS_*"));
Expand Down
151 changes: 151 additions & 0 deletions gas/config/tc-riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -68,6 +68,7 @@ enum riscv_csr_class
CSR_CLASS_DEBUG, /* debug CSR */
CSR_CLASS_H, /* hypervisor */
CSR_CLASS_H_32, /* hypervisor, rv32 only */
CSR_CLASS_P, /* rvp only */
};

/* This structure holds all restricted conditions for a CSR. */
Expand Down Expand Up @@ -926,6 +927,9 @@ riscv_csr_address (const char *csr_name,
case CSR_CLASS_V:
extension = "v";
break;
case CSR_CLASS_P:
extension = "zpn";
break;
case CSR_CLASS_DEBUG:
break;
default:
Expand Down Expand Up @@ -1172,6 +1176,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'Z': /* RS1, CSR number. */
case 'S': /* RS1, floating point. */
case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
case 'g': /* RS1 and RS2 are the same. */
case 'U': /* RS1 and RS2 are the same, floating point. */
USE_BITS (OP_MASK_RS1, OP_SH_RS1);
/* Fall through. */
Expand All @@ -1183,6 +1188,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
case 'l': /* IMM6L */
case 'o': /* ITYPE immediate, load displacement. */
case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break;
Expand Down Expand Up @@ -1214,6 +1220,20 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
goto unknown_validate_operand;
}
break;
case 'n':
switch (*++oparg)
{
case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
case 's': USE_BITS (OP_MASK_RD, OP_SH_RS1); break;
case 't': USE_BITS (OP_MASK_RD, OP_SH_RS2); break;
case '3': used_bits |= ENCODE_PTYPE_IMM3U (-1U); break;
case '4': used_bits |= ENCODE_PTYPE_IMM4U (-1U); break;
case '5': used_bits |= ENCODE_PTYPE_IMM5U (-1U); break;
case '6': used_bits |= ENCODE_PTYPE_IMM6U (-1U); break;
default:
goto unknown_validate_operand;
}
break;
default:
unknown_validate_operand:
as_bad (_("internal: bad RISC-V opcode "
Expand Down Expand Up @@ -2885,6 +2905,17 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
}
continue;

case 'l':
my_getExpression (imm_expr, asarg);
if (imm_expr->X_op != O_constant
|| imm_expr->X_add_number >= xlen
|| imm_expr->X_add_number < 0)
break;
ip->insn_opcode |= ENCODE_ITYPE_IMM6L (imm_expr->X_add_number);
asarg = expr_end;
imm_expr->X_op = O_absent;
continue;

case 'm': /* Rounding mode. */
if (arg_lookup (&asarg, riscv_rm,
ARRAY_SIZE (riscv_rm), &regno))
Expand All @@ -2894,6 +2925,123 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
}
break;

case 'n':
{
switch (*++oparg)
{
case 'd':
if(reg_lookup (&asarg, RCLASS_GPR, &regno))
{
if (xlen == 32 && (regno % 2) != 0)
{
as_bad (_("the number of Rd must be even "
"(limitation of register pair)"));
break;
}
INSERT_OPERAND (RD, *ip, regno);
}
continue;
case 's':
if(reg_lookup (&asarg, RCLASS_GPR, &regno))
{
if (xlen == 32 && (regno % 2) != 0)
{
as_bad (_("the number of Rs1 must be even "
"(limitation of register pair)"));
break;
}
INSERT_OPERAND (RS1, *ip, regno);
}
continue;
case 't':
if(reg_lookup (&asarg, RCLASS_GPR, &regno))
{
if (xlen == 32 && (regno % 2) != 0)
{
as_bad (_("the number of Rs2 must be even "
"(limitation of register pair)"));
break;
}
INSERT_OPERAND (RS2, *ip, regno);
}
continue;


case '3':
{
my_getExpression (imm_expr, asarg);
if (imm_expr->X_op != O_constant
|| imm_expr->X_add_number >= xlen
|| imm_expr->X_add_number < 0)
break;

if(VALID_PTYPE_IMM3U (imm_expr->X_add_number))
{
ip->insn_opcode |= ENCODE_PTYPE_IMM3U (imm_expr->X_add_number);
asarg = expr_end;
imm_expr->X_op = O_absent;
}
}
continue;

case '4':
{
my_getExpression (imm_expr, asarg);
if (imm_expr->X_op != O_constant
|| imm_expr->X_add_number >= xlen
|| imm_expr->X_add_number < 0)
break;

if(VALID_PTYPE_IMM4U (imm_expr->X_add_number))
{
ip->insn_opcode |= ENCODE_PTYPE_IMM4U (imm_expr->X_add_number);
asarg = expr_end;
imm_expr->X_op = O_absent;
}
}
continue;

case '5':
{
my_getExpression (imm_expr, asarg);
if (imm_expr->X_op != O_constant
|| imm_expr->X_add_number >= xlen
|| imm_expr->X_add_number < 0)
break;

if(VALID_PTYPE_IMM3U (imm_expr->X_add_number))
{
ip->insn_opcode |= ENCODE_PTYPE_IMM3U (imm_expr->X_add_number);
asarg = expr_end;
imm_expr->X_op = O_absent;
}
}
continue;

case '6':
{
my_getExpression (imm_expr, asarg);
if (imm_expr->X_op != O_constant
|| imm_expr->X_add_number >= xlen
|| imm_expr->X_add_number < 0)
break;

if(VALID_PTYPE_IMM3U (imm_expr->X_add_number))
{
ip->insn_opcode |= ENCODE_PTYPE_IMM3U (imm_expr->X_add_number);
asarg = expr_end;
imm_expr->X_op = O_absent;
}
}
continue;

default:
goto unknown_riscv_ip_operand;

}
break;
}

case 'P':
case 'Q': /* Fence predecessor/successor. */
if (arg_lookup (&asarg, riscv_pred_succ,
Expand All @@ -2909,6 +3057,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,

case 'd': /* Destination register. */
case 's': /* Source register. */
case 'g': /* RS1 and RS2. */
case 't': /* Target register. */
case 'r': /* RS3 */
if (reg_lookup (&asarg, RCLASS_GPR, &regno))
Expand All @@ -2927,6 +3076,8 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
case 'd':
INSERT_OPERAND (RD, *ip, regno);
break;
case 'g':
INSERT_OPERAND (RS1, *ip, regno);
case 't':
INSERT_OPERAND (RS2, *ip, regno);
break;
Expand Down
25 changes: 25 additions & 0 deletions gas/testsuite/gas/riscv/insn-dsp-zbpbo.d
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Original file line number Diff line number Diff line change
@@ -0,0 +1,25 @@
#as: -march=rv32gc_zbpbo_zpn_zpsf
#source: insn-dsp-zbpbo.s
#objdump: -d

.*:[ ]+file format .*


Disassembly of section .text:

0+000 <dsp>:
[ ]+[0-9a-f]+:[ ]+60061593[ ]+clz[ ]+a1,a2
[ ]+[0-9a-f]+:[ ]+60061593[ ]+clz[ ]+a1,a2
[ ]+[0-9a-f]+:[ ]+76c695b3[ ]+cmix[ ]+a1,a2,a3,a4
[ ]+[0-9a-f]+:[ ]+6ce655b3[ ]+fsr[ ]+a1,a2,a3,a4
[ ]+[0-9a-f]+:[ ]+6c565593[ ]+fsri[ ]+a1,a2,a3,0x5
[ ]+[0-9a-f]+:[ ]+0ad665b3[ ]+max[ ]+a1,a2,a3
[ ]+[0-9a-f]+:[ ]+0ad645b3[ ]+min[ ]+a1,a2,a3
[ ]+[0-9a-f]+:[ ]+08d645b3[ ]+pack[ ]+a1,a2,a3
[ ]+[0-9a-f]+:[ ]+48d645b3[ ]+packu[ ]+a1,a2,a3
[ ]+[0-9a-f]+:[ ]+08d645b3[ ]+pack[ ]+a1,a2,a3
[ ]+[0-9a-f]+:[ ]+48d645b3[ ]+packu[ ]+a1,a2,a3
[ ]+[0-9a-f]+:[ ]+69f65593[ ]+rev[ ]+a1,a2
[ ]+[0-9a-f]+:[ ]+68865593[ ]+rev8.h[ ]+a1,a2
[ ]+[0-9a-f]+:[ ]+68865593[ ]+rev8.h[ ]+a1,a2

16 changes: 16 additions & 0 deletions gas/testsuite/gas/riscv/insn-dsp-zbpbo.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,16 @@
dsp:
clz a1,a2
clz32 a1,a2
cmix a1,a2,a3,a4
fsr a1,a2,a3,a4
fsri a1,a2,a3,5
max a1,a2,a3
min a1,a2,a3
pack a1,a2,a3
packu a1,a2,a3
pktt16 a1,a2,a3
pkbb16 a1,a2,a3
rev a1,a2
rev8.h a1,a2
swap8 a1,a2

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