feat: Handle RISC-V MCAUSE interrupt causes (bit 31)

[Copilot]

When an interrupt (not an exception) triggers a RISC-V panic, MCAUSE has bit 31 set. The previous code looked up the full value (e.g. 0x80000007) in RISCV_EXCEPTIONS, got None, and emitted no annotation — leaving MCAUSE silently unexplained in the monitor output.

Changes

• RISCV_INTERRUPT_CAUSES — new immutable mapping of standard RISC-V M-mode interrupt cause numbers to names (software/timer/external × supervisor/machine)
• get_riscv_exception() — now branches on MCAUSE bit 31:
  • Bit 31 = 0 → exception lookup (unchanged)
  • Bit 31 = 1 → interrupt lookup; named standard causes show "Interrupt: Machine timer interrupt", unknown/platform-specific (cause ≥ 16 on ESP32) show "Interrupt (cause N)"

# Before: no annotation for interrupt-triggered panics
MCAUSE  : 0x80000007

# After
MCAUSE  : 0x80000007 (Interrupt: Machine timer interrupt)
MCAUSE  : 0x80000010 (Interrupt (cause 16))

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