Coreir inline operators

.travis.yml

@@ -29,7 +29,6 @@ before_install:
 install:
 - pip install pytest-cov
 - pip install delegator.py
-- pip install -e git+git://github.com/leonardt/fault.git@hwtypes2#egg=fault
 - pip install -e .
 script:
 - "./scripts/run_tests.sh"

tests/test_coreir/gold/testReg-False-False-False.v

@@ -10,7 +10,7 @@ endmodule
 
 module test (input CLK, input [0:0] In0, output [0:0] Out0, input clk);
 wire [0:0] reg_P_inst0_out;
-coreir_reg #(.clk_posedge(1), .init(1'h0), .width(1)) reg_P_inst0(.clk(clk), .in(In0), .out(reg_P_inst0_out));
+coreir_reg #(.clk_posedge(1'b1), .init(1'h0), .width(1)) reg_P_inst0(.clk(clk), .in(In0), .out(reg_P_inst0_out));
 assign Out0 = reg_P_inst0_out;
 endmodule
 

tests/test_coreir/gold/testReg-False-False-True.v

@@ -13,7 +13,7 @@ endmodule
 
 module test (input ASYNCRESETN, input CLK, input [0:0] In0, output [0:0] Out0, input clk);
 wire [0:0] reg_PR_inst0_out;
-coreir_reg_arst #(.arst_posedge(0), .clk_posedge(1), .init(1'h0), .width(1)) reg_PR_inst0(.arst(ASYNCRESETN), .clk(clk), .in(In0), .out(reg_PR_inst0_out));
+coreir_reg_arst #(.arst_posedge(1'b0), .clk_posedge(1'b1), .init(1'h0), .width(1)) reg_PR_inst0(.arst(ASYNCRESETN), .clk(clk), .in(In0), .out(reg_PR_inst0_out));
 assign Out0 = reg_PR_inst0_out;
 endmodule
 

tests/test_coreir/gold/testReg-False-True-False.v

@@ -13,7 +13,7 @@ endmodule
 
 module test (input ASYNCRESET, input CLK, input [0:0] In0, output [0:0] Out0, input clk);
 wire [0:0] reg_PR_inst0_out;
-coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1'h0), .width(1)) reg_PR_inst0(.arst(ASYNCRESET), .clk(clk), .in(In0), .out(reg_PR_inst0_out));
+coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1'h0), .width(1)) reg_PR_inst0(.arst(ASYNCRESET), .clk(clk), .in(In0), .out(reg_PR_inst0_out));
 assign Out0 = reg_PR_inst0_out;
 endmodule
 

tests/test_coreir/gold/testReg-True-False-False.v

@@ -28,7 +28,7 @@ module Register_has_ce_True_has_reset_False_has_async_reset_False_has_async_rese
 wire [0:0] enable_mux_O;
 wire [0:0] value_out;
 Mux2xOutBits1 enable_mux(.I0(value_out), .I1(I), .O(enable_mux_O), .S(CE));
-coreir_reg #(.clk_posedge(1), .init(1'h0), .width(1)) value(.clk(CLK), .in(enable_mux_O), .out(value_out));
+coreir_reg #(.clk_posedge(1'b1), .init(1'h0), .width(1)) value(.clk(CLK), .in(enable_mux_O), .out(value_out));
 assign O = value_out;
 endmodule
 

tests/test_coreir/gold/testReg-True-False-True.v

@@ -31,7 +31,7 @@ module Register_has_ce_True_has_reset_False_has_async_reset_False_has_async_rese
 wire [0:0] enable_mux_O;
 wire [0:0] value_out;
 Mux2xOutBits1 enable_mux(.I0(value_out), .I1(I), .O(enable_mux_O), .S(CE));
-coreir_reg_arst #(.arst_posedge(0), .clk_posedge(1), .init(1'h0), .width(1)) value(.arst(ASYNCRESETN), .clk(CLK), .in(enable_mux_O), .out(value_out));
+coreir_reg_arst #(.arst_posedge(1'b0), .clk_posedge(1'b1), .init(1'h0), .width(1)) value(.arst(ASYNCRESETN), .clk(CLK), .in(enable_mux_O), .out(value_out));
 assign O = value_out;
 endmodule
 

tests/test_coreir/gold/testReg-True-True-False.v

@@ -31,7 +31,7 @@ module Register_has_ce_True_has_reset_False_has_async_reset_True_has_async_reset
 wire [0:0] enable_mux_O;
 wire [0:0] value_out;
 Mux2xOutBits1 enable_mux(.I0(value_out), .I1(I), .O(enable_mux_O), .S(CE));
-coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1'h0), .width(1)) value(.arst(ASYNCRESET), .clk(CLK), .in(enable_mux_O), .out(value_out));
+coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1'h0), .width(1)) value(.arst(ASYNCRESET), .clk(CLK), .in(enable_mux_O), .out(value_out));
 assign O = value_out;
 endmodule
 

tests/test_coreir/gold/test_latency.v

@@ -8,7 +8,7 @@ module coreir_reg #(parameter width = 1, parameter clk_posedge = 1, parameter in
   assign out = outReg;
 endmodule
 
-module coreir_mem #(parameter has_init = 0, parameter depth = 1, parameter width = 1) (input clk, input [width-1:0] wdata, input [$clog2(depth)-1:0] waddr, input wen, output [width-1:0] rdata, input [$clog2(depth)-1:0] raddr);
+module coreir_mem #(parameter has_init = 1'b0, parameter depth = 1, parameter width = 1) (input clk, input [width-1:0] wdata, input [$clog2(depth)-1:0] waddr, input wen, output [width-1:0] rdata, input [$clog2(depth)-1:0] raddr);
   reg [width-1:0] data[depth-1:0];
   always @(posedge clk) begin
     if (wen) begin
@@ -21,8 +21,8 @@ endmodule
 module RAM256x16 (input CLK, input [7:0] RADDR, output [15:0] RDATA, input [7:0] WADDR, input [15:0] WDATA, input WE);
 wire [15:0] coreir_mem256x16_inst0_rdata;
 wire [15:0] reg_P_inst0_out;
-coreir_mem #(.depth(256), .has_init(0), .width(16)) coreir_mem256x16_inst0(.clk(CLK), .raddr(RADDR), .rdata(coreir_mem256x16_inst0_rdata), .waddr(WADDR), .wdata(WDATA), .wen(WE));
-coreir_reg #(.clk_posedge(1), .init(16'h0000), .width(16)) reg_P_inst0(.clk(CLK), .in(coreir_mem256x16_inst0_rdata), .out(reg_P_inst0_out));
+coreir_mem #(.depth(256), .has_init(1'b0), .width(16)) coreir_mem256x16_inst0(.clk(CLK), .raddr(RADDR), .rdata(coreir_mem256x16_inst0_rdata), .waddr(WADDR), .wdata(WDATA), .wen(WE));
+coreir_reg #(.clk_posedge(1'b1), .init(16'h0000), .width(16)) reg_P_inst0(.clk(CLK), .in(coreir_mem256x16_inst0_rdata), .out(reg_P_inst0_out));
 assign RDATA = reg_P_inst0_out;
 endmodule
 

tests/test_ice40/gold/test_romb_coreir.v

@@ -15,8 +15,8 @@ wire [10:0] const_0_11_out;
 wire [15:0] const_0_16_out;
 wire [10:0] const_1_11_out;
 SB_RAM40_4K #(.INIT_0(256'h0000000000000000000000000000000000000000000000000000000000ff0001), .INIT_1(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000), .READ_MODE(0), .WRITE_MODE(0)) SB_RAM40_4K_inst0(.MASK(const_0_16_out), .RADDR(const_1_11_out), .RCLK(CLK), .RCLKE(bit_const_1_None_out), .RDATA(SB_RAM40_4K_inst0_RDATA), .RE(bit_const_1_None_out), .WADDR(const_0_11_out), .WCLK(CLK), .WCLKE(bit_const_0_None_out), .WDATA(const_0_16_out), .WE(bit_const_0_None_out));
-corebit_const #(.value(0)) bit_const_0_None(.out(bit_const_0_None_out));
-corebit_const #(.value(1)) bit_const_1_None(.out(bit_const_1_None_out));
+corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out));
+corebit_const #(.value(1'b1)) bit_const_1_None(.out(bit_const_1_None_out));
 coreir_const #(.value(11'h000), .width(11)) const_0_11(.out(const_0_11_out));
 coreir_const #(.value(16'h0000), .width(16)) const_0_16(.out(const_0_16_out));
 coreir_const #(.value(11'h001), .width(11)) const_1_11(.out(const_1_11_out));

tests/test_mantle/gold/DefineAdd2_cin_coreir-verilog-inline.v

@@ -0,0 +1,4 @@
+module Add2_cin (input CIN, input [1:0] I0, input [1:0] I1, output [1:0] O);
+assign O = (({1'b0,CIN}) + I0) + I1;
+endmodule
+

tests/test_mantle/gold/DefineAdd2_cin_coreir-verilog.v

@@ -0,0 +1,18 @@
+module coreir_add #(parameter width = 1) (input [width-1:0] in0, input [width-1:0] in1, output [width-1:0] out);
+  assign out = in0 + in1;
+endmodule
+
+module corebit_const #(parameter value = 1) (output out);
+  assign out = value;
+endmodule
+
+module Add2_cin (input CIN, input [1:0] I0, input [1:0] I1, output [1:0] O);
+wire bit_const_0_None_out;
+wire [1:0] coreir_add2_inst0_out;
+wire [1:0] coreir_add2_inst1_out;
+corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out));
+coreir_add #(.width(2)) coreir_add2_inst0(.in0(coreir_add2_inst1_out), .in1(I1), .out(coreir_add2_inst0_out));
+coreir_add #(.width(2)) coreir_add2_inst1(.in0({bit_const_0_None_out,CIN}), .in1(I0), .out(coreir_add2_inst1_out));
+assign O = coreir_add2_inst0_out;
+endmodule
+

tests/test_mantle/gold/DefineAdd2_cin_cout_coreir-verilog-inline.v

@@ -0,0 +1,7 @@
+module Add2_cout_cin (input CIN, output COUT, input [1:0] I0, input [1:0] I1, output [1:0] O);
+wire [2:0] coreir_add3_inst0_out;
+assign coreir_add3_inst0_out = (({1'b0,1'b0,CIN}) + ({1'b0,I0[1],I0[0]})) + ({1'b0,I1[1],I1[0]});
+assign COUT = coreir_add3_inst0_out[2];
+assign O = {coreir_add3_inst0_out[1],coreir_add3_inst0_out[0]};
+endmodule
+

tests/test_mantle/gold/DefineAdd2_cin_cout_coreir-verilog.v

@@ -0,0 +1,19 @@
+module coreir_add #(parameter width = 1) (input [width-1:0] in0, input [width-1:0] in1, output [width-1:0] out);
+  assign out = in0 + in1;
+endmodule
+
+module corebit_const #(parameter value = 1) (output out);
+  assign out = value;
+endmodule
+
+module Add2_cout_cin (input CIN, output COUT, input [1:0] I0, input [1:0] I1, output [1:0] O);
+wire bit_const_0_None_out;
+wire [2:0] coreir_add3_inst0_out;
+wire [2:0] coreir_add3_inst1_out;
+corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out));
+coreir_add #(.width(3)) coreir_add3_inst0(.in0(coreir_add3_inst1_out), .in1({bit_const_0_None_out,I1[1],I1[0]}), .out(coreir_add3_inst0_out));
+coreir_add #(.width(3)) coreir_add3_inst1(.in0({bit_const_0_None_out,bit_const_0_None_out,CIN}), .in1({bit_const_0_None_out,I0[1],I0[0]}), .out(coreir_add3_inst1_out));
+assign COUT = coreir_add3_inst0_out[2];
+assign O = {coreir_add3_inst0_out[1],coreir_add3_inst0_out[0]};
+endmodule
+

tests/test_mantle/gold/DefineAdd2_coreir-verilog-inline.v

@@ -0,0 +1,4 @@
+module coreir_add2_wrapped (input [1:0] I0, input [1:0] I1, output [1:0] O);
+assign O = I0 + I1;
+endmodule
+

tests/test_mantle/gold/DefineAdd2_coreir-verilog.v

@@ -0,0 +1,10 @@
+module coreir_add #(parameter width = 1) (input [width-1:0] in0, input [width-1:0] in1, output [width-1:0] out);
+  assign out = in0 + in1;
+endmodule
+
+module coreir_add2_wrapped (input [1:0] I0, input [1:0] I1, output [1:0] O);
+wire [1:0] coreir_add2_inst0_out;
+coreir_add #(.width(2)) coreir_add2_inst0(.in0(I0), .in1(I1), .out(coreir_add2_inst0_out));
+assign O = coreir_add2_inst0_out;
+endmodule
+

tests/test_mantle/gold/DefineAdd2_cout_coreir-verilog-inline.v

@@ -0,0 +1,7 @@
+module Add2_cout (output COUT, input [1:0] I0, input [1:0] I1, output [1:0] O);
+wire [2:0] coreir_add3_inst0_out;
+assign coreir_add3_inst0_out = ({1'b0,I0[1],I0[0]}) + ({1'b0,I1[1],I1[0]});
+assign COUT = coreir_add3_inst0_out[2];
+assign O = {coreir_add3_inst0_out[1],coreir_add3_inst0_out[0]};
+endmodule
+

tests/test_mantle/gold/DefineAdd2_cout_coreir-verilog.v

@@ -0,0 +1,17 @@
+module coreir_add #(parameter width = 1) (input [width-1:0] in0, input [width-1:0] in1, output [width-1:0] out);
+  assign out = in0 + in1;
+endmodule
+
+module corebit_const #(parameter value = 1) (output out);
+  assign out = value;
+endmodule
+
+module Add2_cout (output COUT, input [1:0] I0, input [1:0] I1, output [1:0] O);
+wire bit_const_0_None_out;
+wire [2:0] coreir_add3_inst0_out;
+corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out));
+coreir_add #(.width(3)) coreir_add3_inst0(.in0({bit_const_0_None_out,I0[1],I0[0]}), .in1({bit_const_0_None_out,I1[1],I1[0]}), .out(coreir_add3_inst0_out));
+assign COUT = coreir_add3_inst0_out[2];
+assign O = {coreir_add3_inst0_out[1],coreir_add3_inst0_out[0]};
+endmodule
+

tests/test_mantle/gold/DefineAdd4_cin_coreir-verilog-inline.v

@@ -0,0 +1,4 @@
+module Add4_cin (input CIN, input [3:0] I0, input [3:0] I1, output [3:0] O);
+assign O = (({1'b0,1'b0,1'b0,CIN}) + I0) + I1;
+endmodule
+

tests/test_mantle/gold/DefineAdd4_cin_coreir-verilog.v

@@ -0,0 +1,18 @@
+module coreir_add #(parameter width = 1) (input [width-1:0] in0, input [width-1:0] in1, output [width-1:0] out);
+  assign out = in0 + in1;
+endmodule
+
+module corebit_const #(parameter value = 1) (output out);
+  assign out = value;
+endmodule
+
+module Add4_cin (input CIN, input [3:0] I0, input [3:0] I1, output [3:0] O);
+wire bit_const_0_None_out;
+wire [3:0] coreir_add4_inst0_out;
+wire [3:0] coreir_add4_inst1_out;
+corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out));
+coreir_add #(.width(4)) coreir_add4_inst0(.in0(coreir_add4_inst1_out), .in1(I1), .out(coreir_add4_inst0_out));
+coreir_add #(.width(4)) coreir_add4_inst1(.in0({bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,CIN}), .in1(I0), .out(coreir_add4_inst1_out));
+assign O = coreir_add4_inst0_out;
+endmodule
+

tests/test_mantle/gold/DefineAdd4_cin_cout_coreir-verilog-inline.v

@@ -0,0 +1,7 @@
+module Add4_cout_cin (input CIN, output COUT, input [3:0] I0, input [3:0] I1, output [3:0] O);
+wire [4:0] coreir_add5_inst0_out;
+assign coreir_add5_inst0_out = (({1'b0,1'b0,1'b0,1'b0,CIN}) + ({1'b0,I0[3],I0[2],I0[1],I0[0]})) + ({1'b0,I1[3],I1[2],I1[1],I1[0]});
+assign COUT = coreir_add5_inst0_out[4];
+assign O = {coreir_add5_inst0_out[3],coreir_add5_inst0_out[2],coreir_add5_inst0_out[1],coreir_add5_inst0_out[0]};
+endmodule
+

tests/test_mantle/gold/DefineAdd4_cin_cout_coreir-verilog.v

@@ -0,0 +1,19 @@
+module coreir_add #(parameter width = 1) (input [width-1:0] in0, input [width-1:0] in1, output [width-1:0] out);
+  assign out = in0 + in1;
+endmodule
+
+module corebit_const #(parameter value = 1) (output out);
+  assign out = value;
+endmodule
+
+module Add4_cout_cin (input CIN, output COUT, input [3:0] I0, input [3:0] I1, output [3:0] O);
+wire bit_const_0_None_out;
+wire [4:0] coreir_add5_inst0_out;
+wire [4:0] coreir_add5_inst1_out;
+corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out));
+coreir_add #(.width(5)) coreir_add5_inst0(.in0(coreir_add5_inst1_out), .in1({bit_const_0_None_out,I1[3],I1[2],I1[1],I1[0]}), .out(coreir_add5_inst0_out));
+coreir_add #(.width(5)) coreir_add5_inst1(.in0({bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,CIN}), .in1({bit_const_0_None_out,I0[3],I0[2],I0[1],I0[0]}), .out(coreir_add5_inst1_out));
+assign COUT = coreir_add5_inst0_out[4];
+assign O = {coreir_add5_inst0_out[3],coreir_add5_inst0_out[2],coreir_add5_inst0_out[1],coreir_add5_inst0_out[0]};
+endmodule
+

tests/test_mantle/gold/DefineAdd4_coreir-verilog-inline.v

@@ -0,0 +1,4 @@
+module coreir_add4_wrapped (input [3:0] I0, input [3:0] I1, output [3:0] O);
+assign O = I0 + I1;
+endmodule
+

tests/test_mantle/gold/DefineAdd4_coreir-verilog.v

@@ -0,0 +1,10 @@
+module coreir_add #(parameter width = 1) (input [width-1:0] in0, input [width-1:0] in1, output [width-1:0] out);
+  assign out = in0 + in1;
+endmodule
+
+module coreir_add4_wrapped (input [3:0] I0, input [3:0] I1, output [3:0] O);
+wire [3:0] coreir_add4_inst0_out;
+coreir_add #(.width(4)) coreir_add4_inst0(.in0(I0), .in1(I1), .out(coreir_add4_inst0_out));
+assign O = coreir_add4_inst0_out;
+endmodule
+

tests/test_mantle/gold/DefineAdd4_cout_coreir-verilog-inline.v

@@ -0,0 +1,7 @@
+module Add4_cout (output COUT, input [3:0] I0, input [3:0] I1, output [3:0] O);
+wire [4:0] coreir_add5_inst0_out;
+assign coreir_add5_inst0_out = ({1'b0,I0[3],I0[2],I0[1],I0[0]}) + ({1'b0,I1[3],I1[2],I1[1],I1[0]});
+assign COUT = coreir_add5_inst0_out[4];
+assign O = {coreir_add5_inst0_out[3],coreir_add5_inst0_out[2],coreir_add5_inst0_out[1],coreir_add5_inst0_out[0]};
+endmodule
+

tests/test_mantle/gold/DefineAdd4_cout_coreir-verilog.v

@@ -0,0 +1,17 @@
+module coreir_add #(parameter width = 1) (input [width-1:0] in0, input [width-1:0] in1, output [width-1:0] out);
+  assign out = in0 + in1;
+endmodule
+
+module corebit_const #(parameter value = 1) (output out);
+  assign out = value;
+endmodule
+
+module Add4_cout (output COUT, input [3:0] I0, input [3:0] I1, output [3:0] O);
+wire bit_const_0_None_out;
+wire [4:0] coreir_add5_inst0_out;
+corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out));
+coreir_add #(.width(5)) coreir_add5_inst0(.in0({bit_const_0_None_out,I0[3],I0[2],I0[1],I0[0]}), .in1({bit_const_0_None_out,I1[3],I1[2],I1[1],I1[0]}), .out(coreir_add5_inst0_out));
+assign COUT = coreir_add5_inst0_out[4];
+assign O = {coreir_add5_inst0_out[3],coreir_add5_inst0_out[2],coreir_add5_inst0_out[1],coreir_add5_inst0_out[0]};
+endmodule
+

tests/test_mantle/gold/DefineAdd8_cin_coreir-verilog-inline.v

@@ -0,0 +1,4 @@
+module Add8_cin (input CIN, input [7:0] I0, input [7:0] I1, output [7:0] O);
+assign O = (({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CIN}) + I0) + I1;
+endmodule
+

tests/test_mantle/gold/DefineAdd8_cin_coreir-verilog.v

@@ -0,0 +1,18 @@
+module coreir_add #(parameter width = 1) (input [width-1:0] in0, input [width-1:0] in1, output [width-1:0] out);
+  assign out = in0 + in1;
+endmodule
+
+module corebit_const #(parameter value = 1) (output out);
+  assign out = value;
+endmodule
+
+module Add8_cin (input CIN, input [7:0] I0, input [7:0] I1, output [7:0] O);
+wire bit_const_0_None_out;
+wire [7:0] coreir_add8_inst0_out;
+wire [7:0] coreir_add8_inst1_out;
+corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out));
+coreir_add #(.width(8)) coreir_add8_inst0(.in0(coreir_add8_inst1_out), .in1(I1), .out(coreir_add8_inst0_out));
+coreir_add #(.width(8)) coreir_add8_inst1(.in0({bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,CIN}), .in1(I0), .out(coreir_add8_inst1_out));
+assign O = coreir_add8_inst0_out;
+endmodule
+

tests/test_mantle/gold/DefineAdd8_cin_cout_coreir-verilog-inline.v

@@ -0,0 +1,7 @@
+module Add8_cout_cin (input CIN, output COUT, input [7:0] I0, input [7:0] I1, output [7:0] O);
+wire [8:0] coreir_add9_inst0_out;
+assign coreir_add9_inst0_out = (({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CIN}) + ({1'b0,I0[7],I0[6],I0[5],I0[4],I0[3],I0[2],I0[1],I0[0]})) + ({1'b0,I1[7],I1[6],I1[5],I1[4],I1[3],I1[2],I1[1],I1[0]});
+assign COUT = coreir_add9_inst0_out[8];
+assign O = {coreir_add9_inst0_out[7],coreir_add9_inst0_out[6],coreir_add9_inst0_out[5],coreir_add9_inst0_out[4],coreir_add9_inst0_out[3],coreir_add9_inst0_out[2],coreir_add9_inst0_out[1],coreir_add9_inst0_out[0]};
+endmodule
+

tests/test_mantle/gold/DefineAdd8_cin_cout_coreir-verilog.v

@@ -0,0 +1,19 @@
+module coreir_add #(parameter width = 1) (input [width-1:0] in0, input [width-1:0] in1, output [width-1:0] out);
+  assign out = in0 + in1;
+endmodule
+
+module corebit_const #(parameter value = 1) (output out);
+  assign out = value;
+endmodule
+
+module Add8_cout_cin (input CIN, output COUT, input [7:0] I0, input [7:0] I1, output [7:0] O);
+wire bit_const_0_None_out;
+wire [8:0] coreir_add9_inst0_out;
+wire [8:0] coreir_add9_inst1_out;
+corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out));
+coreir_add #(.width(9)) coreir_add9_inst0(.in0(coreir_add9_inst1_out), .in1({bit_const_0_None_out,I1[7],I1[6],I1[5],I1[4],I1[3],I1[2],I1[1],I1[0]}), .out(coreir_add9_inst0_out));
+coreir_add #(.width(9)) coreir_add9_inst1(.in0({bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,CIN}), .in1({bit_const_0_None_out,I0[7],I0[6],I0[5],I0[4],I0[3],I0[2],I0[1],I0[0]}), .out(coreir_add9_inst1_out));
+assign COUT = coreir_add9_inst0_out[8];
+assign O = {coreir_add9_inst0_out[7],coreir_add9_inst0_out[6],coreir_add9_inst0_out[5],coreir_add9_inst0_out[4],coreir_add9_inst0_out[3],coreir_add9_inst0_out[2],coreir_add9_inst0_out[1],coreir_add9_inst0_out[0]};
+endmodule
+

tests/test_mantle/gold/DefineAdd8_coreir-verilog-inline.v

@@ -0,0 +1,4 @@
+module coreir_add8_wrapped (input [7:0] I0, input [7:0] I1, output [7:0] O);
+assign O = I0 + I1;
+endmodule
+

tests/test_mantle/gold/DefineAdd8_coreir-verilog.v

@@ -0,0 +1,10 @@
+module coreir_add #(parameter width = 1) (input [width-1:0] in0, input [width-1:0] in1, output [width-1:0] out);
+  assign out = in0 + in1;
+endmodule
+
+module coreir_add8_wrapped (input [7:0] I0, input [7:0] I1, output [7:0] O);
+wire [7:0] coreir_add8_inst0_out;
+coreir_add #(.width(8)) coreir_add8_inst0(.in0(I0), .in1(I1), .out(coreir_add8_inst0_out));
+assign O = coreir_add8_inst0_out;
+endmodule
+

tests/test_mantle/gold/DefineAdd8_cout_coreir-verilog-inline.v

@@ -0,0 +1,7 @@
+module Add8_cout (output COUT, input [7:0] I0, input [7:0] I1, output [7:0] O);
+wire [8:0] coreir_add9_inst0_out;
+assign coreir_add9_inst0_out = ({1'b0,I0[7],I0[6],I0[5],I0[4],I0[3],I0[2],I0[1],I0[0]}) + ({1'b0,I1[7],I1[6],I1[5],I1[4],I1[3],I1[2],I1[1],I1[0]});
+assign COUT = coreir_add9_inst0_out[8];
+assign O = {coreir_add9_inst0_out[7],coreir_add9_inst0_out[6],coreir_add9_inst0_out[5],coreir_add9_inst0_out[4],coreir_add9_inst0_out[3],coreir_add9_inst0_out[2],coreir_add9_inst0_out[1],coreir_add9_inst0_out[0]};
+endmodule
+