pzbcm_async_fifo

pzbcm_async_fifo

https://github.com/pezy-computing/pzbcm/tree/master/pzbcm_async_fifo

Overview

This implements a dual clock asynchronous FIFO.

Parameters

name	type/width	default value
WIDTH	int	8
TYPE	type	logic [WIDTH-1:0]
STAGES	int	`PZBCM_SYNCHRONIZER_DEFAULT_STAGES
DEPTH	int	See below
THRESHOLD	int	DEPTH
USE_OUT_DATA_RESET	bit	0
INITIAL_OUT_DATA	TYPE	TYPE'(0)

• WIDTH
  • Width of input/output data.
• TYPE
  • Type of input/output data. logic[WIDTH-1:0] is its default.
• STAGES
  • This is specify how many FFs used for CDC.
• DEPTH
  • This is specify how many entries in the FIFO. Its default value is calcurated by the calc_default_depth function.
• THRESHOLD
  • This is specify the threshold value for the almost full status.
• USE_OUT_DATA_RESET
  • If this is set to 1 the output FF will be reset when the reset signal is asserted.
• INITIAL_OUT_DATA
  • This is to specify the reset value of the output FF.

IO ports

name	direction	width/type	note
is_clk	input	1	source side clock
is_rst_n	input	1	source side reset (async/low active)
os_almost_full	output	1	indicate almost all FIFO entries are used
os_full	output	1	indicate all FIFO entries are used
is_push	input	1	is_data is pushed into the FIFO when this port is asserted
is_data	input	TYPE	input data
id_clk	input	1	destination side clock
id_rst_n	input	1	destination side reset (async/low active)
id_empty	output	1	indicate no FIFO entries are not used
id_pop	input	1	od_data is popped from the FIFO when this port is asserted
od_data	output	TYPE	output data