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    301 repositories

    • pulp-nnx

      Public
      C
      •
      Apache License 2.0
      •2•6•0•2•Updated Apr 15, 2025Apr 15, 2025

    • picobello

      Public
      whatever it means
      SystemVerilog
      •
      Other
      •2•6•7•1•Updated Apr 15, 2025Apr 15, 2025

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •21•103•1•7•Updated Apr 15, 2025Apr 15, 2025

    • redmule

      Public
      SystemVerilog
      •
      Other
      •16•55•1•6•Updated Apr 15, 2025Apr 15, 2025

    • llvm-project

      Public
      C++
      •13k•8•7•1•Updated Apr 14, 2025Apr 14, 2025

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •61•74•19•7•Updated Apr 14, 2025Apr 14, 2025

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •49•289•3•5•Updated Apr 14, 2025Apr 14, 2025

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •63•247•10•20•Updated Apr 14, 2025Apr 14, 2025

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •12•13•5•3•Updated Apr 12, 2025Apr 12, 2025

    • hwpe-stream

      Public
      IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •20•19•2•4•Updated Apr 12, 2025Apr 12, 2025

    • carfield

      Public
      A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
      casicfpgasimulationriscvsystemverilogsafety-criticalheterogeneous-computingmixed-criticality-systems
      Tcl
      •
      Other
      •17•91•18•4•Updated Apr 12, 2025Apr 12, 2025

    • cv32e40x

      Public
      4 stage, in-order, compute RISC-V core based on the CV32E40P
      SystemVerilog
      •
      Other
      •53•1•0•0•Updated Apr 12, 2025Apr 12, 2025

    • riscv-opcodes

      Public
      RISC-V Opcodes
      Python
      •
      Other
      •319•7•0•4•Updated Apr 11, 2025Apr 11, 2025

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •287•1.3k•46•12•Updated Apr 11, 2025Apr 11, 2025

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •18•72•2•2•Updated Apr 11, 2025Apr 11, 2025

    • axi_llc

      Public
      SystemVerilog
      •
      Other
      •16•25•3•6•Updated Apr 10, 2025Apr 10, 2025

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •747•19•0•6•Updated Apr 10, 2025Apr 10, 2025

    • astral

      Public
      A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
      cfpgaspaceacceleratorriscvsystemverilogmulticoresafety-criticalheterogeneous-computing
      Tcl
      •
      Other
      •17•6•0•6•Updated Apr 10, 2025Apr 10, 2025

    • control-pulp

      Public
      C
      •
      Other
      •2•3•1•1•Updated Apr 10, 2025Apr 10, 2025

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •32•191•15•6•Updated Apr 10, 2025Apr 10, 2025

    • clic

      Public
      RISC-V fast interrupt controller
      interruptrisc-vclic
      SystemVerilog
      •
      Apache License 2.0
      •4•21•7•3•Updated Apr 8, 2025Apr 8, 2025

    • chimera

      Public
      Python
      •
      Other
      •4•16•9•5•Updated Apr 8, 2025Apr 8, 2025

    • artistic

      Public
      An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
      asicrenderinggdsii
      Python
      •
      Apache License 2.0
      •1•13•0•0•Updated Apr 8, 2025Apr 8, 2025

    • hyperbus

      Public
      SystemVerilog
      •
      Other
      •3•22•2•1•Updated Apr 8, 2025Apr 8, 2025

    • Deeploy

      Public
      DNN Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •
      Apache License 2.0
      •12•35•8•5•Updated Apr 8, 2025Apr 8, 2025

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •26•88•5•4•Updated Apr 4, 2025Apr 4, 2025

    • regression_tests

      Public
      C
      •17•8•3•1•Updated Apr 2, 2025Apr 2, 2025

    • DeepQuant

      Public
      A Python library for true quantization of neural networks
      Python
      •
      Apache License 2.0
      •0•4•0•0•Updated Apr 1, 2025Apr 1, 2025

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •45•292•28•9•Updated Mar 31, 2025Mar 31, 2025

    • dutctl

      Public
      A Flexible Open-Source Framework for Rapid Bring-Up, Characterization, and Remote Operation of Custom-Silicon RISC-V SoCs
      0•1•0•0•Updated Mar 31, 2025Mar 31, 2025