[RDNA2] Port rdna_extras onto vLLM v0.31.0 (rdna_extra/v0.31.0)

CMakeLists.txt

@@ -1478,6 +1478,7 @@ if(VLLM_GPU_LANG STREQUAL "HIP")
     "csrc/rocm/torch_bindings.cpp"
     "csrc/rocm/skinny_gemms.cu"
     "csrc/rocm/skinny_gemms_int4.cu"
+    "csrc/rocm/rdna_allreduce.cu"
     "csrc/rocm/attention.cu")
   set(VLLM_ROCM_EXT_FLAGS ${VLLM_GPU_FLAGS})
 
@@ -1493,7 +1494,8 @@ if(VLLM_GPU_LANG STREQUAL "HIP")
     message(STATUS "Building skinny_gemms for archs: ${VLLM_SKINNY_ARCHES}")
     set(VLLM_SKINNY_SRC
       "csrc/rocm/skinny_gemms.cu"
-      "csrc/rocm/skinny_gemms_int4.cu")
+      "csrc/rocm/skinny_gemms_int4.cu"
+      "csrc/rocm/moe_resident_decode.cu")
     hipify_sources_target(VLLM_SKINNY_HIP_SRCS _rocm_C_skinny "${VLLM_SKINNY_SRC}")
     unset(_VLLM_LAST_HIPIFY_TARGET)
     add_library(_rocm_C_skinny OBJECT ${VLLM_SKINNY_HIP_SRCS})
@@ -1512,6 +1514,46 @@ if(VLLM_GPU_LANG STREQUAL "HIP")
     list(APPEND VLLM_ROCM_EXT_FLAGS "-DVLLM_SKIP_SKINNY_GEMMS")
   endif()
 
+  set(VLLM_ROCM_HAS_GFX1030 OFF)
+  message(STATUS "[DEBUG] VLLM_GPU_ARCHES='${VLLM_GPU_ARCHES}'")
+  if(VLLM_GPU_ARCHES MATCHES "gfx1030")
+    set(VLLM_ROCM_HAS_GFX1030 ON)
+    list(APPEND VLLM_ROCM_EXT_SRC
+      "csrc/rocm/q_gemm_rdna2.cu"
+      "csrc/rocm/q_gemm_rdna2_prefill.cu"
+      "csrc/rocm/w4a8_sdot4_rdna2.cu"
+      "csrc/rocm/rdna_fused_glue.cu"
+      "csrc/rocm/hc_prefill_rdna2.cu"
+      "csrc/rocm/fa_rdna2.cu"
+      "csrc/rocm/gemm_w8a8_fp8_dense_rdna2.cu"
+      "csrc/rocm/moe_q_gemm_rdna2.cu"
+      "csrc/rocm/moe_w4a8_rdna2.cu"
+      "csrc/rocm/gdn_decode_rdna2.cu"
+      "csrc/rocm/causal_conv1d_rdna2.cu"
+      "csrc/rocm/gdn_prefill_prep_rdna2.cu"
+      "csrc/rocm/gdn_prefill_kkt_rdna2.cu"
+      "csrc/rocm/gdn_prefill_solve_wy_rdna2.cu"
+      "csrc/rocm/gdn_prefill_delta_h_rdna2.cu"
+      "csrc/rocm/gdn_prefill_o_rdna2.cu"
+      "csrc/rocm/mxfp4_dot2_moe.cu"
+      "csrc/rocm/mxfp4_dot2_dense.cu"
+      "csrc/rocm/moe_w8a16_rdna2.cu"
+      "csrc/rocm/q_gemm_w8a16_fp8_rdna2.cu"
+      "csrc/rocm/mrope_rdna2.cu"
+      "csrc/rocm/hc_rdna2.cu"
+      "csrc/rocm/qsa_rdna2.cu"
+      "csrc/rocm/ple_short_conv_rdna2.cu"
+      # DeepSeek-V4 RDNA kernels (csrc/rocm/rdna/<feature>/ layout).
+      "csrc/rocm/rdna/dsv4/indexer_mqa_logits.cu"
+      "csrc/rocm/rdna/dsv4/kv_insert.cu"
+      "csrc/rocm/rdna/dsv4/mhc.cu"
+      "csrc/rocm/rdna/dsv4/sparse_mla_decode.cu")
+    # moe_w8a16_fp8_rdna2.cu excluded from gfx1030 build (namespace parser
+    # error per rdna2_extras commit 9ac015d0a9 / AGENTS.md 2026-08-05).
+    # MoE experts fall back to existing CompressedTensorsWNA16MoEMethod
+    # (INT4) or scaled_mm dispatch.
+  endif()
+
   set(VLLM_ROCM_HAS_GFX1100 OFF)
   if(VLLM_GPU_ARCHES MATCHES "gfx1100")
     set(VLLM_ROCM_HAS_GFX1100 ON)
@@ -1521,6 +1563,17 @@ if(VLLM_GPU_LANG STREQUAL "HIP")
       "csrc/rocm/moe_q_gemm_rdna3.cu")
   endif()
 
+  # EXL3 dot kernels are RDNA-generic (gfx1030 + gfx1100). Listed once,
+  # unconditionally: the __gfx1030__/__gfx1100__ device-pass gate inside
+  # each .cu decides whether the non-empty kernel is emitted for the arch
+  # being compiled.
+  list(APPEND VLLM_ROCM_EXT_SRC
+    "csrc/rocm/exl3_dot2_moe.cu"
+    "csrc/rocm/exl3_dot2_dense.cu"
+    "csrc/rocm/exl3_dot2_dequant.cu"
+    "csrc/rocm/exl3_hadamard.cu"
+    "csrc/rocm/layernorm.cu")
+
   define_extension_target(
     _rocm_C
     DESTINATION vllm
@@ -1537,9 +1590,24 @@ if(VLLM_GPU_LANG STREQUAL "HIP")
     target_compile_definitions(_rocm_C PRIVATE VLLM_SKIP_SKINNY_GEMMS)
   endif()
 
+  if(VLLM_ROCM_HAS_GFX1030)
+    target_compile_definitions(_rocm_C PRIVATE VLLM_ROCM_GFX1030)
+  endif()
+
   if(VLLM_ROCM_HAS_GFX1100)
     target_compile_definitions(_rocm_C PRIVATE VLLM_ROCM_GFX1100)
   endif()
+  # torch 2.13 + ROCm 7.2 shim: cusolver was renamed to hipsolver.
+  # Provide cusolver_common.h shim + hipsolver include path globally.
+  if(DEFINED ENV{ROCM_PATH})
+    target_include_directories(_rocm_C SYSTEM PRIVATE $ENV{ROCM_PATH}/include)
+  endif()
+  if(EXISTS "$ENV{ROCM_PATH}/include/cusolver_common.h")
+    target_compile_options(_rocm_C PRIVATE -include $ENV{ROCM_PATH}/include/cusolver_common.h)
+  endif()
+  # GCC 15 + torch 2.13 + ROCm 7.2 namespace parser workaround
+  # (qdq_4_rdna2.cuh:22 false-positive on namespace vllm {)
+  target_compile_options(_rocm_C PRIVATE -fpermissive)
 endif()
 
 # Must run after the last HIP `define_extension_target` so every extension

bench_results/2026-09-29_tp4-fp-aroff/SUMMARY.md

@@ -0,0 +1,114 @@
+# TP=4 W4A16 FULL-HIP, `RDNA_AR=0`, FULL_AND_PIECEWISE — bring-up result
+
+**Date:** 2026-09-29
+**Tree:** `vllm-rdna-0.28.0` @ `8de502574` (`w4a8-wiring`) → `par1-cs25:/home/chenco_adm/vllm-rdna-0.28.0`
+**Model:** `cyankiwi/Qwen3.8-27B-AWQ-INT4` (compressed-tensors W4A16)
+**Venv:** `/home/chenco_adm/Apps/vllm/venv-7.14.0_0.28.0`
+**Run dir (remote):** `/home/chenco_adm/w4a8_runs/2026-09-29_tp4-fp-aroff/`
+
+## Verdict
+
+- **Boot clean: NO.** The chassis hard-reset during the post-compile / cudagraph-capture phase. New `PCI SERR` logged.
+- **Coherence: not measured** (server never reached READY).
+- **16k/1k numbers: not measured** (never READY).
+- **Fork AR is exonerated:** the reset reproduces with `VLLM_RDNA_AR=0`; active all-reduce was `['PYNCCL']` only.
+
+## What ran (exact env/args)
+
+Driver `tools/rdna2_028/fp_aroff_27b.sh` (new) → launcher `scripts/serve_gfx1030_27b_dense.sh` (new `RDNA_AR` knob):
+
+```
+MTP=0 W4A8=0 RDNA_AR=0 EAGER=0 ATTN=fa TP=4 PORT=18240
+KV=8000000000 SEQS=8 MAXBAT=2048 CG_MODE=FULL_AND_PIECEWISE
+VLLM_CACHE_ROOT=$T/cache/hip-fp-aroff
+TORCHINDUCTOR_CACHE_DIR=$T/cache/hip-fp-aroff/inductor
+TRITON_CACHE_DIR=$T/cache/hip-fp-aroff/triton
+TORCH_EXTENSIONS_DIR=$T/cache/hip-fp-aroff/extensions
+```
+
+Effective serve args (from `serve.log`):
+`--attention-backend RDNA_ATTN --tensor-parallel-size 4 --dtype float16 --block-size 1024
+--kv-cache-memory-bytes 8000000000 --gpu-memory-utilization 0.9 --max-num-batched-tokens 2048
+--max-num-seqs 8 --enable-prefix-caching --mamba-cache-mode align --language-model-only
+--compilation-config {"cudagraph_mode":"FULL_AND_PIECEWISE","cudagraph_capture_sizes":[1,2,4,8],"compile_ranges_endpoints":[]}`
+No `--max-model-len` (model default).
+
+Caches were wiped (`rm -rf $T/cache/hip-fp-aroff`) before launch, so no contaminated W4A8 graph
+could replay. `serve.log` confirms the fresh root: `cache/hip-fp-aroff/torch_compile_cache/...`.
+
+## Timeline
+
+| Time (CEST) | Event |
+|---|---|
+| 14:38:00 | serve launched (driver preflight: PCI SERR baseline = **12**, uptime 57 min) |
+| 14:39:11 | weights loaded, 5.01 GiB/GPU (all 4 ranks) |
+| 14:39:06 | all-reduce selection: active `['PYNCCL']` |
+| 14:39:26 | Dynamo bytecode transform: 13.20 s |
+| 14:40:14 | inductor graph for compile range (1, 2048): 46.87 s |
+| 14:40:18 | `torch.compile took 65.40 s`; `[rdna2_persist] eager grow` ×4; Triton deprecation warnings |
+| 14:40:12 → 14:48:13 | `shm_broadcast: No available shared memory broadcast block found in 60 seconds` every 60 s (worker busy post-compile) |
+| 14:48:13 | last worker log line |
+| ~14:46:47 → 14:50:42 | host hangs / resets; no clean-shutdown journal entries |
+| **14:50:42** | **new SEL `e68 | Critical Interrupt | PCI SERR | Asserted`** |
+| 14:51:25 | system boot (journal boot id 0) |
+
+**Cold-compile duration:** inductor `torch.compile` = **65.40 s** (Dynamo 13.20 s + range compile 46.87 s);
+model load ≈ 5 s. The reset came ≈10.5 min *after* compile finished, in the silent post-compile
+worker phase (cudagraph capture / full-graph replay prep), i.e. the previous "the long compile window
+resets the chassis" framing is too narrow — the inductor compile itself completed quickly.
+
+## IPMI / SEL delta
+
+- Before (14:38:00): `PCI SERR` = **12**, `Critical Interrupt` = 17, `Correctable ECC` = 10.
+- After (post-reboot): `PCI SERR` = **13**.
+- New entry: `e68 | 09/29/2026 | 02:50:42 PM CEST | Critical Interrupt | PCI SERR | Asserted`.
+- **Note the id is reused** — the SEL already had an old `e68` (09/23, `PCI PERR`), so a set-diff by
+  record id shows no new id; the reliable signal is the count 12→13 plus the new `14:50:42` timestamp.
+- Unlike the earlier resets (e64+e65 and e66+e67 both paired with `Memory | Correctable ECC | CPU 0 DIMM 0`),
+  **e68 has no paired ECC entry** — this reset was a pure PCI SERR. (Matches the DIMM-ECC-vs-fabric
+  ambiguity: the DIMM is a suspect, but not proven for this event.)
+
+## Fork-marker audit (over the partial `serve.log`)
+
+| Marker | Expected | Observed |
+|---|---|---|
+| `RDNA2 W4A8 sdot4 path active` | absent | **absent** (0) |
+| `W4A8-DEBUG` | absent | **absent** (0) |
+| `rdna_ar:` lines | none (`VLLM_RDNA_AR=0`) | **none** (0) |
+| `Custom allreduce force-enabled` | absent | **absent** (0) |
+| active all-reduce backends | PYNCCL only | `Using ['PYNCCL'] all-reduce backends … out of potential backends: ['RDNA_ONESHOT', …]` |
+| attention backend | RDNA_ATTN | `Using RDNA_ATTN backend` |
+
+`RDNA_ONESHOT` appears only in the *potential* backends list, never in the active list — the knob
+(`RDNA_AR=0` → `VLLM_RDNA_AR=0`) works and the fork PCIe-peer AR is definitively out of the picture.
+
+## Conclusion
+
+The TP=4 F&P hard reset is **not caused by the fork's PCIe-peer all-reduce.** It reproduces with the
+AR path disabled and the only active collective is RCCL/PYNCCL. The reset occurs during the
+cudagraph-capture/post-compile phase and is accompanied by a fabric-level `PCI SERR` (no DIMM ECC
+companion this time). Next investigation axes: DIMM/fabric stability (the DIMM was already the
+suspect), and the TP=4 FULL_AND_PIECEWISE capture path itself — no further runs were attempted per
+the "a reset is evidence, stop and report" rule.
+
+## Evidence files
+
+`remote_logs/` (copied verbatim from the box):
+- `driver.log`, `ipmi.log` — driver progress + pre-run IPMI snapshot
+- `serve.log` — partial serve log (122 lines, through 14:48:13)
+- `before.sel.txt` — 14:38:00 SEL snapshot (SERR=12)
+- `after_reboot.sel.txt`, `after_reboot.elist.txt` — post-reboot SEL (SERR=13, includes e68)
+- `../args.txt` — non-default args + all-reduce backend line
+
+## Reproduction
+
+```bash
+rsync -avz --exclude='.git/' --exclude='cache/' --exclude='*.abi3.so' \
+  -e "ssh -i ~/.ssh/id_ed25519_ansible" \
+  ./vllm-rdna-0.28.0/ chenco_adm@par1-cs25:/home/chenco_adm/vllm-rdna-0.28.0/
+ssh -i ~/.ssh/id_ed25519_ansible chenco_adm@par1-cs25 \
+  'cd /home/chenco_adm/vllm-rdna-0.28.0 && TAG=2026-09-29_tp4-fp-aroff bash tools/rdna2_028/fp_aroff_27b.sh'
+```
+
+**Do not re-run without a hardware-stability answer** — this is the 4th reset in the same class today
+(e63/e65/e67/e68).

bench_results/2026-09-29_tp4-fp-aroff/args.txt

@@ -0,0 +1,2 @@
+(APIServer pid=49285) INFO 09-29 14:38:21 [api_utils.py:286] non-default args: {'model_tag': '/home/chenco_adm/.cache/huggingface/hub/models--cyankiwi--Qwen3.8-27B-AWQ-INT4/snapshots/63768c10df38c0395e12ef49edac1bd539eaeeea', 'host': '127.0.0.1', 'port': 18240, 'model': '/home/chenco_adm/.cache/huggingface/hub/models--cyankiwi--Qwen3.8-27B-AWQ-INT4/snapshots/63768c10df38c0395e12ef49edac1bd539eaeeea', 'dtype': 'float16', 'served_model_name': ['q27d'], 'attention_backend': 'RDNA_ATTN', 'tensor_parallel_size': 4, 'block_size': 1024, 'gpu_memory_utilization': 0.9, 'kv_cache_memory_bytes': 8000000000, 'enable_prefix_caching': True, 'mamba_cache_mode': 'align', 'language_model_only': True, 'limit_mm_per_prompt': {'image': 1}, 'mm_processor_kwargs': {'max_pixels': 1605632}, 'max_num_batched_tokens': 2048, 'max_num_seqs': 8, 'compilation_config': {'mode': None, 'debug_dump_path': None, 'cache_dir': '', 'compile_cache_save_format': 'binary', 'backend': 'inductor', 'custom_ops': [], 'ir_enable_torch_wrap': None, 'splitting_ops': None, 'compile_mm_encoder': False, 'cudagraph_mm_encoder': False, 'encoder_cudagraph_token_budgets': [], 'encoder_cudagraph_max_vision_items_per_batch': 0, 'encoder_cudagraph_max_frames_per_batch': None, 'compile_sizes': None, 'compile_ranges_endpoints': [], 'inductor_compile_config': {'enable_auto_functionalized_v2': False, 'combo_kernels': True, 'benchmark_combo_kernel': True}, 'inductor_passes': {}, 'cudagraph_mode': <CUDAGraphMode.FULL_AND_PIECEWISE: (2, 1)>, 'cudagraph_num_of_warmups': 0, 'cudagraph_capture_sizes': [1, 2, 4, 8], 'cudagraph_copy_inputs': False, 'cudagraph_specialize_lora': True, 'use_inductor_graph_partition': None, 'pass_config': {}, 'max_cudagraph_capture_size': None, 'dynamic_shapes_config': {'type': <DynamicShapesType.BACKED: 'backed'>, 'evaluate_guards': False, 'assume_32_bit_indexing': False}, 'local_cache_dir': None, 'fast_moe_cold_start': None, 'static_all_moe_layers': []}}
+(Worker pid=49867) INFO 09-29 14:39:06 [cuda_communicator.py:299] Using ['PYNCCL'] all-reduce backends (in dispatch order) for group 'tp:0' out of potential backends: ['RDNA_ONESHOT', 'NCCL_SYMM_MEM', 'QUICK_REDUCE', 'FLASHINFER', 'AITER_CUSTOM', 'CUSTOM', 'SYMM_MEM', 'PYNCCL'].