odyssey bmc backend sbefifo device tree changes

This commit is to cater for odyssey DDR5 device tree changes.

Every proc chip will be associated with 8 ddr5 ocmb chips
which are accessed through sbefifo.

SBEFifo are configured as /dev/sbefifoXYY where X is the proc
number and YY as the port number.

Based on the fsi path found on the everest with ddr5 configuration
"/i2cr101/slave@00:00/raw" configured the same in the device tree
for kernel-fsi for each associated DDR5 chip.

Ensured that existing DDR4 devices does not have any impact.

Configured device path of the DDR5 OCMB odyssey chips in the
bmc backend device tree

get and put scom on ocmb chips will be using the newly configured
ocmb device path for sbefifo access

Tested:
Ensured that the new ocmb odyssesy SBE targets are added
and are probed verified both fsi and sbefifo probe is done
sucessfully

pdbg target path is /hmfsiocmb@101/sbefifo-ocmb@101
pdbg compatible is ibm,kernel-sbefifo
pdbg device-path is /dev/sbefifo101
pdbg_target_probe  status is  0
kernel_fsi_probe device_path /i2cr101/slave@00:00/raw
kernel_fsi_probe path /sys/class/fsi-master//i2cr101/slave@00:00/raw success probed
sbefifo_connect fifo_path /dev/sbefifo101

pdbg_target_probe class name is sbefifo
pdbg target path is /proc0/fsi/sbefifo@2400
pdbg compatible is ibm,kernel-sbefifo
pdbg device-path is /dev/sbefifo1
pdbg_target_probe  status is  0
kernel_fsi_probe device_path /fsi0/slave@00:00/raw
kernel_fsi_probe path /sys/class/fsi-master//fsi0/slave@00:00/raw success probed
sbefifo_connect fifo_path /dev/sbefifo1

Signed-off-by: Marri Devender Rao <[email protected]>
Change-Id: Ibf6c32ec578730ac79d7d732e545ed3be6c9ed0c

bmc-sbefifo.dts.m4

@@ -36,6 +36,7 @@ define(`SBEFIFO',
 	};
 ')dnl
 
+
 dnl
 dnl FSI_PRE([addr], [index], [path-index])
 dnl
@@ -81,6 +82,43 @@ define(`HMFSI',
 	};
 ')dnl
 
+dnl
+dnl SBEFIFO_ODY([index], [proc], [path-index], [port] [])
+dnl
+define(`SBEFIFO_ODY',
+`
+	sbefifo-ody@$3$4{ /* Bogus address */
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		compatible = "ibm,kernel-sbefifo";
+		reg = <0x0 0x$1 0x8000>; /*dummy to fix dts warning*/
+		index = <0x$1>;
+		proc = <0x$2>;
+		port = <$4>;
+		device-path = "/dev/sbefifo$3$4";
+	};
+
+')dnl
+
+dnl
+dnl HMFSI_ODY([index], [proc], [proc+1], [port])
+dnl
+define(`HMFSI_ODY',
+`
+	hmfsi-ody@$3$4 {
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		compatible = "ibm,kernel-fsi";
+		device-path = "/i2cr$3$4/slave@00:00/raw";
+		reg = <0x0 0x$1 0x8000>; /*dummy to fix dts warning*/
+		index = <0x$1>;
+		proc = <0x$2>;
+		port = <$4>;
+
+		SBEFIFO_ODY($1, $2, $3, $4)
+	};
+')dnl
+
 dnl
 dnl BMC_I2CBUS([index])
 dnl
@@ -131,4 +169,77 @@ define(`BMC_I2CBUS',
 	HMFSI(400000, 7, 7, 8)
 
 	FSI_POST()
+
+	HMFSI_ODY(0, 0, 1, 00)
+	HMFSI_ODY(1, 0, 1, 01)
+	HMFSI_ODY(2, 0, 1, 10)
+	HMFSI_ODY(3, 0, 1, 11)
+	HMFSI_ODY(4, 0, 1, 12)
+	HMFSI_ODY(5, 0, 1, 13)
+	HMFSI_ODY(6, 0, 1, 14)
+	HMFSI_ODY(7, 0, 1, 15)
+
+	HMFSI_ODY(0, 1, 2, 02)
+	HMFSI_ODY(1, 1, 2, 03)
+	HMFSI_ODY(2, 1, 2, 10)
+	HMFSI_ODY(3, 1, 2, 11)
+	HMFSI_ODY(4, 1, 2, 14)
+	HMFSI_ODY(5, 1, 2, 15)
+	HMFSI_ODY(6, 1, 2, 16)
+	HMFSI_ODY(7, 1, 2, 17)
+
+
+	HMFSI_ODY(0, 2, 3, 00)
+	HMFSI_ODY(1, 2, 3, 01)
+	HMFSI_ODY(2, 2, 3, 10)
+	HMFSI_ODY(3, 2, 3, 11)
+	HMFSI_ODY(4, 2, 3, 12)
+	HMFSI_ODY(5, 2, 3, 13)
+	HMFSI_ODY(6, 2, 3, 14)
+	HMFSI_ODY(7, 2, 3, 15)
+
+	HMFSI_ODY(0, 3, 4, 02)
+	HMFSI_ODY(1, 3, 4, 03)
+	HMFSI_ODY(2, 3, 4, 10)
+	HMFSI_ODY(3, 3, 4, 11)
+	HMFSI_ODY(4, 3, 4, 14)
+	HMFSI_ODY(5, 3, 4, 15)
+	HMFSI_ODY(6, 3, 4, 16)
+	HMFSI_ODY(7, 3, 4, 17)
+
+	HMFSI_ODY(0, 4, 5, 00)
+	HMFSI_ODY(1, 4, 5, 01)
+	HMFSI_ODY(2, 4, 5, 10)
+	HMFSI_ODY(3, 4, 5, 11)
+	HMFSI_ODY(4, 4, 5, 12)
+	HMFSI_ODY(5, 4, 5, 13)
+	HMFSI_ODY(6, 4, 5, 14)
+	HMFSI_ODY(7, 4, 5, 15)
+
+	HMFSI_ODY(0, 5, 6, 02)
+	HMFSI_ODY(1, 5, 6, 03)
+	HMFSI_ODY(2, 5, 6, 10)
+	HMFSI_ODY(3, 5, 6, 11)
+	HMFSI_ODY(4, 5, 6, 14)
+	HMFSI_ODY(5, 5, 6, 15)
+	HMFSI_ODY(6, 5, 6, 16)
+	HMFSI_ODY(7, 5, 6, 17)
+
+	HMFSI_ODY(0, 6, 7, 00)
+	HMFSI_ODY(1, 6, 7, 01)
+	HMFSI_ODY(2, 6, 7, 10)
+	HMFSI_ODY(3, 6, 7, 11)
+	HMFSI_ODY(4, 6, 7, 12)
+	HMFSI_ODY(5, 6, 7, 13)
+	HMFSI_ODY(6, 6, 7, 14)
+	HMFSI_ODY(7, 6, 7, 15)
+
+	HMFSI_ODY(0, 7, 8, 02)
+	HMFSI_ODY(1, 7, 8, 03)
+	HMFSI_ODY(2, 7, 8, 10)
+	HMFSI_ODY(3, 7, 8, 11)
+	HMFSI_ODY(4, 7, 8, 14)
+	HMFSI_ODY(5, 7, 8, 15)
+	HMFSI_ODY(6, 7, 8, 16)
+	HMFSI_ODY(7, 7, 8, 17)
 };