cpu:aarch64: Extending support for BRGEMM General and 1x1 Forward Convolution

[kasturedeeksha]

Description

This commit expands ARM SVE support for JIT SVE BRGEMM general and 1x1 forward convolution in FP32, introducing compatibility with various vector lengths. The changes made are for implementing different ARM SVE vector lengths.

Major code changes:

1. generalized code by adding template with isa as argument.
2. set predicate registers according to SVE length.

Checklist

General

• Do all unit and benchdnn tests (make test and make test_benchdnn_*) pass locally for each commit? Yes
  Test output is same with and without this commit.

1. make test output:

98% tests passed, 3 tests failed out of 195

Total Test time (real) = 1375.38 sec

The following tests FAILED:
        149 - test_graph_unit_dnnl_conv_usm_cpu (Failed)
        154 - test_graph_unit_dnnl_large_partition_usm_cpu (Failed)
        176 - test_benchdnn_modeC_graph_ci_cpu (Failed)
Errors while running CTest

• Have you formatted the code using clang-format? Yes
  cc : @kawakami-k