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Small Signadyne driver updates #6

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Mar 22, 2017
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47 changes: 15 additions & 32 deletions qcodes/instrument_drivers/keysight/SD_common/SD_AWG.py
Original file line number Diff line number Diff line change
Expand Up @@ -103,22 +103,6 @@ def __init__(self, name, chassis, slot, channels, triggers, **kwargs):
# Get-commands
#

def get_pxi_trigger(self, pxi_trigger, verbose=False):
"""
Returns the digital value of the specified PXI trigger

Args:
pxi_trigger (int): PXI trigger number (4000 + Trigger No.)
verbose (bool): boolean indicating verbose mode

Returns:
value (int): Digital value with negated logic, 0 (ON) or 1 (OFF),
or negative numbers for errors
"""
value = self.awg.PXItriggerRead(pxi_trigger)
value_name = 'pxi_trigger number {}'.format(pxi_trigger)
return result_parser(value, value_name, verbose)

def get_trigger_io(self, verbose=False):
"""
Reads and returns the trigger input
Expand Down Expand Up @@ -233,16 +217,6 @@ def set_channel_wave_shape(self, wave_shape, channel_number):
"""
self.awg.channelWaveShape(channel_number, wave_shape)

def set_pxi_trigger(self, value, pxi_trigger):
"""
Sets the digital value of the specified PXI trigger

Args:
pxi_trigger (int): PXI trigger number (4000 + Trigger No.)
value (int): Digital value with negated logic, 0 (ON) or 1 (OFF)
"""
self.awg.PXItriggerWrite(pxi_trigger, value)

def set_trigger_io(self, value):
"""
Sets the trigger output. The trigger must be configured as output using
Expand Down Expand Up @@ -499,7 +473,7 @@ def awg_from_file(self, awg_number, waveform_file, trigger_mode, start_delay, cy
start_delay (int): defines the delay between trigger and wf launch
given in multiples of 10ns.
cycles (int): number of times the waveform is repeated once launched
negative = infinite repeats
zero = infinite repeats
prescaler (int): waveform prescaler value, to reduce eff. sampling rate

Returns:
Expand Down Expand Up @@ -530,7 +504,7 @@ def awg_from_array(self, awg_number, trigger_mode, start_delay, cycles, prescale
start_delay (int): defines the delay between trigger and wf launch
given in multiples of 10ns.
cycles (int): number of times the waveform is repeated once launched
negative = infinite repeats
zero = infinite repeats
prescaler (int): waveform prescaler value, to reduce eff. sampling rate
waveform_type (int): waveform type
waveform_data_a (array): array with waveform points
Expand Down Expand Up @@ -672,7 +646,7 @@ def awg_trigger_multiple(self, awg_mask):
provided it is configured with VI/HVI Trigger.

Args:
awg_mask (int): Mask to select the awgs to stop (LSB is awg 0, bit 1 is awg 1 etc.)
awg_mask (int): Mask to select the awgs to be triggered (LSB is awg 0, bit 1 is awg 1 etc.)
"""
self.awg.AWGtriggerMultiple(awg_mask)

Expand All @@ -692,7 +666,10 @@ def new_waveform_from_file(self, waveform_file):
waveform (SD_Wave): pointer to the waveform object,
or negative numbers for errors
"""
return self.wave.newFromFile(waveform_file)
wave = keysightSD1.SD_Wave()
result = wave.newFromFile(waveform_file)
result_parser(result)
return wave

def new_waveform_from_double(self, waveform_type, waveform_data_a, waveform_data_b=None):
"""
Expand All @@ -709,7 +686,10 @@ def new_waveform_from_double(self, waveform_type, waveform_data_a, waveform_data
waveform (SD_Wave): pointer to the waveform object,
or negative numbers for errors
"""
return self.wave.newFromArrayDouble(waveform_type, waveform_data_a, waveform_data_b)
wave = keysightSD1.SD_Wave()
result = wave.newFromArrayDouble(waveform_type, waveform_data_a, waveform_data_b)
result_parser(result)
return wave

def new_waveform_from_int(self, waveform_type, waveform_data_a, waveform_data_b=None):
"""
Expand All @@ -726,7 +706,10 @@ def new_waveform_from_int(self, waveform_type, waveform_data_a, waveform_data_b=
waveform (SD_Wave): pointer to the waveform object,
or negative numbers for errors
"""
return self.wave.newFromArrayInteger(waveform_type, waveform_data_a, waveform_data_b)
wave = keysightSD1.SD_Wave()
result = wave.newFromArrayInteger(waveform_type, waveform_data_a, waveform_data_b)
result_parser(result)
return wave

def get_waveform_status(self, waveform, verbose=False):
value = waveform.getStatus()
Expand Down
64 changes: 63 additions & 1 deletion qcodes/instrument_drivers/keysight/SD_common/SD_Module.py
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@
'(http://www.keysight.com/main/software.jspx?ckey=2784055)')


def result_parser(value, name, verbose=False):
def result_parser(value, name='result', verbose=False):
"""
This method is used for parsing the result in the get-methods.
For values that are non-negative, the value is simply returned.
Expand Down Expand Up @@ -171,6 +171,68 @@ def get_open(self, verbose=False):
value_name = 'open'
return result_parser(value, value_name, verbose)

def get_pxi_trigger(self, pxi_trigger, verbose=False):
"""
Returns the digital value of the specified PXI trigger

Args:
pxi_trigger (int): PXI trigger number (4000 + Trigger No.)
verbose (bool): boolean indicating verbose mode

Returns:
value (int): Digital value with negated logic, 0 (ON) or 1 (OFF),
or negative numbers for errors
"""
value = self.SD_module.PXItriggerRead(pxi_trigger)
value_name = 'pxi_trigger number {}'.format(pxi_trigger)
return result_parser(value, value_name, verbose)

#
# Set-commands
#

def set_pxi_trigger(self, value, pxi_trigger):
"""
Sets the digital value of the specified PXI trigger

Args:
pxi_trigger (int): PXI trigger number (4000 + Trigger No.)
value (int): Digital value with negated logic, 0 (ON) or 1 (OFF)
"""
self.SD_module.PXItriggerWrite(pxi_trigger, value)

#
# FPGA related functions
#

def get_fpga_pc_port(self, port, data_size, address, address_mode, access_mode, verbose=False):
"""
Reads data at the PCport FPGA Block

Args:
port (int): PCport number
data_size (int): number of 32-bit words to read (maximum is 128 words)
address (int): address that wil appear at the PCport interface
address_mode (int): ?? not in the docs
access_mode (int): ?? not in the docs
"""
data = self.SD_module.FPGAreadPCport(port, data_size, address, address_mode, access_mode)
value_name = 'data at PCport {}'.format(port)
return result_parser(data, value_name, verbose)

def set_fpga_pc_port(self, port, data, address, address_mode, access_mode, verbose=False):
"""
Writes data at the PCport FPGA Block

Args:
port (int): PCport number
data (array): array of integers containing the data
address (int): address that wil appear at the PCport interface
address_mode (int): ?? not in the docs
access_mode (int): ?? not in the docs
"""
self.SD_module.FPGAwritePCport(port, data, address, address_mode, access_mode, verbose)

#
# The methods below are not used for setting or getting parameters, but can be used in the test functions of the
# test suite e.g. The main reason they are defined is to make this driver more complete
Expand Down