feat(SSA): optimize array_get on slice intrinsics

[asterite]

Description

Problem

Resolves #10296

Summary

Additional Context

Documentation

Check one:

• No documentation needed.
• Documentation included in this PR.
• [For Experimental Features] Documentation to be submitted in a separate PR.

PR Checklist

• I have tested the changes locally.
• I have formatted the changes with Prettier and/or cargo fmt on default settings.

[github-actions]

Changes to Brillig bytecode sizes

Generated at commit: e76339d1c0bf34bb3270d72ce13be885ff998032, compared to commit: dd8b7e81c3249cbaef557b734220aac44e361090

🧾 Summary (10% most significant diffs)

Program	Brillig opcodes (+/-)	%
slice_dynamic_index_inliner_max	-37 ✅	-2.28%
slice_dynamic_index_inliner_zero	-37 ✅	-2.28%

---

Full diff report 👇

Program	Brillig opcodes (+/-)	%
slices_inliner_max	1,673 (-12)	-0.71%
slices_inliner_zero	1,633 (-12)	-0.73%
regression_capacity_tracker_inliner_max	213 (-2)	-0.93%
regression_capacity_tracker_inliner_min	213 (-2)	-0.93%
regression_capacity_tracker_inliner_zero	213 (-2)	-0.93%
slice_dynamic_index_inliner_min	2,120 (-30)	-1.40%
slice_dynamic_index_inliner_max	1,589 (-37)	-2.28%
slice_dynamic_index_inliner_zero	1,589 (-37)	-2.28%

[github-actions]

Changes to circuit sizes

Generated at commit: e76339d1c0bf34bb3270d72ce13be885ff998032, compared to commit: dd8b7e81c3249cbaef557b734220aac44e361090

🧾 Summary (10% most significant diffs)

Program	ACIR opcodes (+/-)	%	Circuit size (+/-)	%
slice_dynamic_insert	-12 ✅	-30.77%	-32 ✅	-17.88%

---

Full diff report 👇

Program	ACIR opcodes (+/-)	%	Circuit size (+/-)	%
slice_dynamic_insert	27 (-12)	-30.77%	147 (-32)	-17.88%

[github-actions]

Changes to number of Brillig opcodes executed

Generated at commit: e76339d1c0bf34bb3270d72ce13be885ff998032, compared to commit: dd8b7e81c3249cbaef557b734220aac44e361090

🧾 Summary (10% most significant diffs)

Program	Brillig opcodes (+/-)	%
slice_dynamic_index_inliner_max	-25 ✅	-0.70%
slice_dynamic_index_inliner_zero	-25 ✅	-0.70%

---

Full diff report 👇

Program	Brillig opcodes (+/-)	%
slices_inliner_zero	2,722 (-8)	-0.29%
slices_inliner_max	2,524 (-8)	-0.32%
regression_capacity_tracker_inliner_max	566 (-2)	-0.35%
regression_capacity_tracker_inliner_min	566 (-2)	-0.35%
regression_capacity_tracker_inliner_zero	566 (-2)	-0.35%
slice_dynamic_index_inliner_min	4,547 (-20)	-0.44%
slice_dynamic_index_inliner_max	3,559 (-25)	-0.70%
slice_dynamic_index_inliner_zero	3,559 (-25)	-0.70%

[github-actions]

⚠️ Performance Alert ⚠️

Possible performance regression was detected for benchmark 'Test Suite Duration'.
Benchmark result of this commit is worse than the previous benchmark result exceeding threshold 1.20.

Benchmark suite	Current: 0f8413a	Previous: dd8b7e8	Ratio
test_report_zkpassport_noir-ecdsa_	4 s	2 s	2

This comment was automatically generated by workflow using github-action-benchmark.

CC: @TomAFrench

[asterite]

Closing until #10206 is merged.