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rx_top.qsf
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rx_top.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
# Date created = 22:50:58 April 13, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# rx_top_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6F17C8
set_global_assignment -name TOP_LEVEL_ENTITY rx_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:50:58 APRIL 13, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_E1 -to CLK
set_location_assignment PIN_C3 -to LED_Out[7]
set_location_assignment PIN_A2 -to LED_Out[6]
set_location_assignment PIN_B3 -to LED_Out[5]
set_location_assignment PIN_A3 -to LED_Out[4]
set_location_assignment PIN_B4 -to LED_Out[3]
set_location_assignment PIN_A4 -to LED_Out[2]
set_location_assignment PIN_B5 -to LED_Out[1]
set_location_assignment PIN_A5 -to LED_Out[0]
set_location_assignment PIN_R16 -to RSTn
set_location_assignment PIN_P15 -to RX_En_Sig
set_location_assignment PIN_C15 -to RX_Pin_In
set_location_assignment PIN_D15 -to LED_Out[8]
set_location_assignment PIN_D16 -to LED_Out[9]
set_location_assignment PIN_F15 -to LED_Out[10]
set_location_assignment PIN_F16 -to LED_Out[11]
set_location_assignment PIN_G15 -to LED_Out[12]
set_location_assignment PIN_G16 -to LED_Out[13]
set_location_assignment PIN_L13 -to LED_Out[14]
set_location_assignment PIN_L14 -to LED_Out[15]
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_location_assignment PIN_R1 -to DAC_CLK
set_location_assignment PIN_T2 -to DAC_DATA[9]
set_location_assignment PIN_P1 -to DAC_DATA[8]
set_location_assignment PIN_P2 -to DAC_DATA[7]
set_location_assignment PIN_N1 -to DAC_DATA[6]
set_location_assignment PIN_N2 -to DAC_DATA[5]
set_location_assignment PIN_L1 -to DAC_DATA[4]
set_location_assignment PIN_L2 -to DAC_DATA[3]
set_location_assignment PIN_K1 -to DAC_DATA[2]
set_location_assignment PIN_K2 -to DAC_DATA[1]
set_location_assignment PIN_J1 -to DAC_DATA[0]
set_location_assignment PIN_N13 -to SW_Sin_In
set_global_assignment -name VERILOG_FILE choose_wave_module.v
set_global_assignment -name VERILOG_FILE dac_module.v
set_global_assignment -name VERILOG_FILE sinrom1.v
set_global_assignment -name VERILOG_FILE rx_top.v
set_global_assignment -name VERILOG_FILE detect_module.v
set_global_assignment -name VERILOG_FILE rx_bps_module.v
set_global_assignment -name VERILOG_FILE rx_control_module.v
set_global_assignment -name VERILOG_FILE LED_Display_module.v
set_global_assignment -name VERILOG_FILE kw_crl.v
set_global_assignment -name QIP_FILE sinrom1.qip
set_global_assignment -name QIP_FILE pll_clk.qip
set_location_assignment PIN_N14 -to SW_VPP
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top