Add FSMC driver for STM32

- Update CMake accordingly - Enable external SDRAM for STM32F429I-DISCOVERY - Updater STM32F429I-DISCOVERY target common with new RAM size Signed-off-by: josesimoes <[email protected]>
nanoframework · Apr 7, 2018 · a8bfb29 · a8bfb29
1 parent d7d7d57
commit a8bfb29
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Showing 22 changed files with 927 additions and 1,225 deletions.
diff --git a/src/CLR/Core/Execution.cpp b/src/CLR/Core/Execution.cpp
@@ -155,6 +155,14 @@ HRESULT CLR_RT_ExecutionEngine::AllocateHeaps()
         CLR_RT_HeapCluster* hc   = (CLR_RT_HeapCluster*)                                 heapFirstFree;
         CLR_UINT32          size =                      (heapFree < c_HeapClusterSize) ? heapFree : c_HeapClusterSize;
 
+#if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_1_HeapBlocksAndUnlink
+
+        CLR_Debug::Printf( "Heap Cluster information\r\n");
+        CLR_Debug::Printf( "Start:       %08x\r\n", (size_t)heapFirstFree);
+        CLR_Debug::Printf( "Free:        %08x\r\n", (size_t)heapFree);
+        CLR_Debug::Printf( "Block size:  %d\r\n", sizeof(CLR_RT_HeapBlock));
+
+#endif
         ///
         /// Speed up heap initialization for devices with very large heaps > 1MB
         /// Exponentially increase the size of a default heap block

diff --git a/src/HAL/Include/nanoHAL_v2.h b/src/HAL/Include/nanoHAL_v2.h
@@ -9,6 +9,7 @@
 
 #include <stdio.h>
 #include <stdbool.h>
+#include <nanoWeak.h>
 
 typedef enum SYSTEM_STATE
 {
@@ -151,6 +152,10 @@ extern "C" {
 void nanoHAL_Initialize_C();
 void HeapLocation_C(unsigned char** baseAddress, unsigned int* sizeInBytes);
 
+// Call to the external memory configuration and initialization function
+// If a target has external memory it has to provide the implementation for it.
+void Target_ExternalMemoryInit();
+
 #ifdef __cplusplus
 }
 #endif

diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/CMakeLists.txt b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/CMakeLists.txt
@@ -93,6 +93,8 @@ add_executable(
     ${NANOCLR_PROJECT_NAME}.elf
 
     "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c"
+    # the next one is required is the target implements and it's using external memory
+    "${CMAKE_CURRENT_SOURCE_DIR}/target_external_memory.c"
 
     ${COMMON_PROJECT_SOURCES}
     ${NANOCLR_PROJECT_SOURCES}

diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/STM32F429xI_CLR.ld b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/STM32F429xI_CLR.ld
@@ -24,6 +24,7 @@ MEMORY
     ram5        : org = 0x40024000, len = 4k                    /* BCKP SRAM */
     ram6        : org = 0x00000000, len = 0
     ram7        : org = 0x00000000, len = 0
+    ext_ram     : org = 0xD0000000, len = 8M                    /* external SDRAM */
 }
 
 /* For each data/text section two region are defined, a virtual region
@@ -71,6 +72,6 @@ REGION_ALIAS("BSS_RAM", ram0);
 REGION_ALIAS("HEAP_RAM", ram4);
 
 /* RAM region to be used for the nanoFramework CLR managed heap.*/
-REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0);
+REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ext_ram);
 
 INCLUDE rules.ld
diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf_nf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf_nf.h
@@ -16,5 +16,9 @@
 #define HAL_USE_STM32_FLASH         TRUE
 #endif
 
-#endif // _HALCONF_NF_H_
+//  Enables the FSMC subsystem.
+#if !defined(HAL_USE_FSMC)
+#define HAL_USE_FSMC                TRUE
+#endif
 
+#endif // _HALCONF_NF_H_
diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/main.c b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/main.c
@@ -36,6 +36,10 @@ int main(void) {
   // main() is executing with absolute priority but interrupts are already enabled.
   osKernelInitialize();
 
+  // config and init external memory
+  // this has to be called after osKernelInitialize, otherwise an hard fault will occur
+  Target_ExternalMemoryInit();
+
   //  Initializes a serial-over-USB CDC driver.
   sduObjectInit(&SDU1);
   sduStart(&SDU1, &serusbcfg);

diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf_nf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf_nf.h
@@ -6,5 +6,20 @@
 #ifndef _MCUCONF_NF_H_
 #define _MCUCONF_NF_H_
 
+
+/*
+ * FSMC driver system settings.
+ */
+#define STM32_FSMC_USE_FSMC1                TRUE
+#define STM32_FSMC_FSMC1_IRQ_PRIORITY       10
+#define STM32_FSMC_DMA_CHN                  0x03010201
+
+/*
+ * FSMC SDRAM driver system settings.
+ */
+#define STM32_USE_FSMC_SDRAM                TRUE
+#define STM32_SDRAM_USE_FSMC_SDRAM1         FALSE
+#define STM32_SDRAM_USE_FSMC_SDRAM2         TRUE
+
 #endif // _MCUCONF_NF_H_
 
diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_common.h.in b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_common.h.in
@@ -18,9 +18,9 @@
 // they also must be coherent with what's in the linker file for nanoBooter and nanoCLR
 
 // RAM base address 
-#define RAM1_MEMORY_StartAddress        ((uint32_t)0x200000C0)
+#define RAM1_MEMORY_StartAddress        ((uint32_t)0xD0000000)
 // RAM size 
-#define RAM1_MEMORY_Size                ((uint32_t)0x00030000)
+#define RAM1_MEMORY_Size                ((uint32_t)0x00800000)
 
 // FLASH base address
 #define FLASH1_MEMORY_StartAddress      ((uint32_t)0x08000000)

diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_external_memory.c b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_external_memory.c
@@ -0,0 +1,106 @@
+//
+// Copyright (c) 2018 The nanoFramework project contributors
+// See LICENSE file in the project root for full license information.
+//
+
+#include <ch.h>
+#include "hal.h"
+#include "fsmc_sdram_lld.h"
+
+
+// SDRAM Mode definition register defines
+#define FMC_SDCMR_MRD_BURST_LENGTH_1             ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_BURST_LENGTH_2             ((uint16_t)0x0001)
+#define FMC_SDCMR_MRD_BURST_LENGTH_4             ((uint16_t)0x0002)
+#define FMC_SDCMR_MRD_BURST_LENGTH_8             ((uint16_t)0x0004)
+#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL      ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED     ((uint16_t)0x0008)
+#define FMC_SDCMR_MRD_CAS_LATENCY_2              ((uint16_t)0x0020)
+#define FMC_SDCMR_MRD_CAS_LATENCY_3              ((uint16_t)0x0030)
+#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)
+
+// FMC_ReadPipe_Delay
+#define FMC_ReadPipe_Delay_0               ((uint32_t)0x00000000)
+#define FMC_ReadPipe_Delay_1               ((uint32_t)0x00002000)
+#define FMC_ReadPipe_Delay_2               ((uint32_t)0x00004000)
+#define FMC_ReadPipe_Delay_Mask            ((uint32_t)0x00006000)
+
+// FMC_Read_Burst
+#define FMC_Read_Burst_Disable             ((uint32_t)0x00000000)
+#define FMC_Read_Burst_Enable              ((uint32_t)0x00001000)
+#define FMC_Read_Burst_Mask                ((uint32_t)0x00001000)
+
+// FMC_SDClock_Period
+#define FMC_SDClock_Disable                ((uint32_t)0x00000000)
+#define FMC_SDClock_Period_2               ((uint32_t)0x00000800)
+#define FMC_SDClock_Period_3               ((uint32_t)0x00000C00)
+#define FMC_SDClock_Period_Mask            ((uint32_t)0x00000C00)
+
+// FMC_ColumnBits_Number
+#define FMC_ColumnBits_Number_8b           ((uint32_t)0x00000000)
+#define FMC_ColumnBits_Number_9b           ((uint32_t)0x00000001)
+#define FMC_ColumnBits_Number_10b          ((uint32_t)0x00000002)
+#define FMC_ColumnBits_Number_11b          ((uint32_t)0x00000003)
+
+// FMC_RowBits_Number
+#define FMC_RowBits_Number_11b             ((uint32_t)0x00000000)
+#define FMC_RowBits_Number_12b             ((uint32_t)0x00000004)
+#define FMC_RowBits_Number_13b             ((uint32_t)0x00000008)
+
+// FMC_SDMemory_Data_Width
+#define FMC_SDMemory_Width_8b                ((uint32_t)0x00000000)
+#define FMC_SDMemory_Width_16b               ((uint32_t)0x00000010)
+#define FMC_SDMemory_Width_32b               ((uint32_t)0x00000020)
+
+// FMC_InternalBank_Number
+#define FMC_InternalBank_Number_2          ((uint32_t)0x00000000)
+#define FMC_InternalBank_Number_4          ((uint32_t)0x00000040)
+
+// FMC_CAS_Latency
+#define FMC_CAS_Latency_1                  ((uint32_t)0x00000080)
+#define FMC_CAS_Latency_2                  ((uint32_t)0x00000100)
+#define FMC_CAS_Latency_3                  ((uint32_t)0x00000180)
+
+// FMC_Write_Protection
+#define FMC_Write_Protection_Disable       ((uint32_t)0x00000000)
+#define FMC_Write_Protection_Enable        ((uint32_t)0x00000200)
+
+#define SDRAM_SIZE       (8 * 1024 * 1024)
+#define SDRAM_START      ((void *)FSMC_Bank6_MAP_BASE)
+
+
+// SDRAM driver configuration structure.
+static const SDRAMConfig sdram_cfg = {
+  .sdcr = (uint32_t) FMC_ColumnBits_Number_8b |
+                     FMC_RowBits_Number_12b |
+                     FMC_SDMemory_Width_16b |
+                     FMC_InternalBank_Number_4 |
+                     FMC_CAS_Latency_3 |
+                     FMC_Write_Protection_Disable |
+                     FMC_SDClock_Period_2 |
+                     FMC_Read_Burst_Enable |
+                     FMC_ReadPipe_Delay_1,
+  .sdtr = (uint32_t) (2   - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles)
+                     (7 <<  4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns))
+                     (4 <<  8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns))
+                     (7 << 12) | // FMC_RowCycleDelay = 7 (TRC:  min=70 (7x11.11ns))
+                     (3 << 16) | // FMC_WriteRecoveryTime = 2 (TWR:  min=1+ 7ns (1+1x11.11ns))
+                     (2 << 20) | // FMC_RPDelay = 2 (TRP:  20ns => 2x11.11ns)
+                     (2 << 24),  // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns)
+ // NRFS = 4-1
+  .sdcmr = (3 << 5) | (FMC_SDCMR_MRD_BURST_LENGTH_2 |
+                       FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |
+                       FMC_SDCMR_MRD_CAS_LATENCY_3 |
+                       FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |
+                       FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9,
+
+  .sdrtr = (uint32_t)(683 << 1),
+};
+
+void Target_ExternalMemoryInit()
+{
+    fsmcSdramInit();
+    fsmcSdramStart(&SDRAMD, &sdram_cfg);
+}
diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/STM32F76xx_CLR.ld b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/STM32F76xx_CLR.ld
@@ -30,7 +30,6 @@ MEMORY
     ram5        : org = 0x40024000, len = 4k                        /* BCKP SRAM */
     ram6        : org = 0x00000000, len = 0
     ram7        : org = 0x00000000, len = 0
-    sram        : org = 0xC0000000, len = 2M
 }
 
 /* For each data/text section two region are defined, a virtual region

diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf_nf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf_nf.h
@@ -16,9 +16,4 @@
 #define HAL_USE_STM32_FLASH         TRUE
 #endif
 
-// Enables the Flexible Memory Controller subsystem.
-#if !defined(HAL_USE_FSMC)
-#define HAL_USE_FSMC                TRUE
-#endif
-
 #endif // _HALCONF_NF_H_
diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/main.c b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/main.c
@@ -15,50 +15,6 @@
 #include <nanoPAL_BlockStorage.h>
 #include <targetPAL.h>
 
-#define FSMC_BASE             ((uint32_t)0x60000000) /*!< FSMC base address */
-
-#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-
-// SDRAM driver configuration structure
-// need this definition here because it depends on the specifics of the target
-#if (HAL_USE_FSMC == TRUE)
-static const SDRAMConfig sdram_cfg = 
-{
-  .sdcr = (uint32_t) FMC_SDRAM_COLUMN_BITS_NUM_8 |
-                     FMC_SDRAM_ROW_BITS_NUM_12 |
-                     FMC_SDRAM_MEM_BUS_WIDTH_16 |
-                     FMC_SDRAM_INTERN_BANKS_NUM_4 |
-                     FMC_SDRAM_CAS_LATENCY_2 |
-                     FMC_SDRAM_WRITE_PROTECTION_DISABLE |
-                     FMC_SDRAM_CLOCK_PERIOD_2 |
-                     FMC_SDRAM_RBURST_ENABLE |
-                     FMC_SDRAM_RPIPE_DELAY_0,
-  .sdtr = (uint32_t) ((2 - 1) | // FSMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles)
-                     ((6 - 1) <<  4) | // FSMC_ExitSelfRefreshDelay = 6 (TXSR: min=70ns (6x11.11ns))
-                     ((4 - 1) <<  8) | // FSMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns))
-                     ((6 - 1) << 12) | // FSMC_RowCycleDelay = 6 (TRC:  min=70 (6x11.11ns))
-                     ((2 - 1) << 16) | // FSMC_WriteRecoveryTime = 2 (TWR:  min=1+ 7ns (1+1x11.11ns))
-                     ((2 - 1) << 20) | // FSMC_RPDelay = 2 (TRP:  20ns => 2x11.11ns)
-                     ((2 - 1) << 24)),  // FSMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns)
-  /* NRFS = 4-1*/
-  .sdcmr = (SDRAM_MODEREG_BURST_LENGTH_1 |
-                       SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
-                       SDRAM_MODEREG_CAS_LATENCY_2 |
-                       SDRAM_MODEREG_OPERATING_MODE_STANDARD |
-                       SDRAM_MODEREG_WRITEBURST_MODE_SINGLE) << 9,
-
-  // Set the refresh rate counter
-  // (15.62 us x Freq) - 20
-  .sdrtr = (uint32_t)(1292 << 1),
-};
-
-#define SDRAM_BANK_ADDR                 ((uint32_t)0xC0000000)
-#define WRITE_READ_ADDR     ((uint32_t)0x0800)
-#endif
-
-uint32_t __attribute__((section (".myBufSection"))) aTxBuffer[255];
-uint32_t aRxBuffer[255];
-
 // need to declare the Receiver thread here
 osThreadDef(ReceiverThread, osPriorityNormal, 2048, "ReceiverThread");
 // declare CLRStartup thread here 
@@ -80,47 +36,6 @@ int main(void) {
   // main() is executing with absolute priority but interrupts are already enabled.
   osKernelInitialize();
 
-  #if (HAL_USE_FSMC == TRUE)
-
-  /* Enable I-Cache */
-  SCB_EnableICache();
-
-  /* Enable D-Cache */
-  SCB_EnableDCache();
-
-
-  fsmcSdramInit();
-  fsmcSdramStart(&SDRAMD, &sdram_cfg);
-
-  uint32_t tmpIndex = 0;
-
-  /* Put in global buffer different values */
-  for (tmpIndex = 0; tmpIndex < 255; tmpIndex++ )
-  {
-    aTxBuffer[tmpIndex] = tmpIndex + 0xA244250F;
-  }
-
-uint32_t uwIndex = 0;
-  // /* Write data to the SDRAM memory */
-  // for (uwIndex = 0; uwIndex < 255; uwIndex++)
-  // {
-  //   (*((volatile unsigned long *) (SDRAM_BANK_ADDR + 4*uwIndex))) = aTxBuffer[uwIndex];
-  // }
-
-  /* Read back data from the SDRAM memory */
-  for (uwIndex = 0; uwIndex < 255; uwIndex++)
-  {
-    aRxBuffer[uwIndex] = (*((volatile unsigned long *) (SDRAM_BANK_ADDR + 4*uwIndex)));
-  }
-
-
-  //*(__IO uint16_t*) (SDRAM_BANK_ADDR ) = 0xDEAD;
-
-
-volatile int testValue = *(__IO uint16_t*) (SDRAM_BANK_ADDR);
-
-  #endif
-
   //  Initializes a serial-over-USB CDC driver.
   sduObjectInit(&SDU1);
   sduStart(&SDU1, &serusbcfg);

diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf_nf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf_nf.h
@@ -6,27 +6,4 @@
 #ifndef _MCUCONF_NF_H_
 #define _MCUCONF_NF_H_
 
-// FSMC driver system settings
-#define STM32_FSMC_USE_FSMC1              TRUE
-#define STM32_FSMC_FSMC1_IRQ_PRIORITY     10
-
-// FSMC NAND driver system settings
-#define STM32_NAND_USE_FSMC_NAND1        FALSE
-#define STM32_NAND_USE_FSMC_NAND2        FALSE
-
-// FCM SDRAM driver system settings
-#define STM32_USE_FSMC_SDRAM             TRUE
-#define STM32_SDRAM_USE_FSMC_SDRAM1      TRUE
-#define STM32_SDRAM_USE_FSMC_SDRAM2      FALSE
-
-// FCM SRAM driver system settings
-#define STM32_USE_FSMC_SRAM              FALSE
-#define STM32_SRAM_USE_FSMC_SRAM1        FALSE
-#define STM32_SRAM_USE_FSMC_SRAM2        FALSE
-#define STM32_SRAM_USE_FSMC_SRAM3        FALSE
-#define STM32_SRAM_USE_FSMC_SRAM4        FALSE
-
-// FCM PC card driver system settings
-#define STM32_USE_FSMC_PCCARD            FALSE
-
 #endif // _MCUCONF_NF_H_