Fix and update for STM32 flash driver

- Need to correct the flash pointers and access to flash registers Signed-off-by: josesimoes <[email protected]>
nanoframework · Mar 14, 2018 · 73c69f3 · 73c69f3
1 parent 7a1b881
commit 73c69f3
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Showing 4 changed files with 44 additions and 26 deletions.
diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv1/flash_lld.c b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv1/flash_lld.c
@@ -92,16 +92,19 @@ int flash_lld_write(uint32_t startAddress, uint32_t length, const uint8_t* buffe
             // NOTE: assuming that the supply voltage is able to cope with half-word programming
             if((endAddress - cursor) >= 2)
             {
-                *((__IO uint16_t*)cursor++) = *((uint16_t*)buffer++);
+                *(__IO uint16_t*)cursor = *((uint16_t*)buffer);
 
                 // update flash and buffer pointers by the 'extra' byte that was programmed
-                cursor++;
-                buffer++;
+                cursor += 2;
+                buffer += 2;
             }
             else
             {
                 // program single byte
-                *((__IO uint8_t*)cursor++) = *((uint8_t*)buffer);
+                *(__IO uint8_t*)cursor = *buffer;
+
+                // update flash pointer by the 'extra' byte that was programmed
+                cursor += 2;
             }
 
             // wait for program operation to be completed 

diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2/flash_lld.c b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2/flash_lld.c
@@ -166,13 +166,13 @@ int flash_lld_write(uint32_t startAddress, uint32_t length, const uint8_t* buffe
             if((endAddress - cursor) >= 2)
             {
                 // clear the program size mask
-                CLEAR_BIT(FLASH->CR, CR_PSIZE_MASK);
+                FLASH->CR &= CR_PSIZE_MASK;
                 // set the size of of the programming word to HALF WORD
-                SET_BIT(FLASH->CR, FLASH_PSIZE_HALF_WORD);
+                FLASH->CR |= FLASH_PSIZE_HALF_WORD;
                 // proceed to program the flash by setting the PG Bit
-                SET_BIT(FLASH->CR, FLASH_CR_PG);
+                FLASH->CR |= FLASH_CR_PG;
 
-                *((__IO uint16_t*)cursor++) = *((uint16_t*)buffer++);
+                *(__IO uint16_t*)cursor = *((uint16_t*)buffer);
 
 #if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F745xx) || defined(STM32F767xx) || \
     defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F722xx) || \
@@ -182,21 +182,21 @@ int flash_lld_write(uint32_t startAddress, uint32_t length, const uint8_t* buffe
                 __DSB();
 #endif
                 // update flash and buffer pointers by the 'extra' byte that was programmed
-                cursor++;
-                buffer++;
+                cursor += 2;
+                buffer += 2;
             }
             else
             {
                 // program single byte
 
                 // clear the program size mask
-                CLEAR_BIT(FLASH->CR, CR_PSIZE_MASK);
+                FLASH->CR &= CR_PSIZE_MASK;
                 // set the size of of the programming word to BYTE
-                SET_BIT(FLASH->CR, FLASH_PSIZE_BYTE);
+                FLASH->CR |= FLASH_PSIZE_BYTE;
                 // proceed to program the flash by setting the PG Bit
-                SET_BIT(FLASH->CR, FLASH_CR_PG);
+                FLASH->CR |= FLASH_CR_PG;
 
-                *((__IO uint8_t*)cursor++) = *((uint8_t*)buffer);
+                *(__IO uint8_t*)cursor = *buffer;
 
 #if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F745xx) || defined(STM32F767xx) || \
     defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F722xx) || \
@@ -205,6 +205,9 @@ int flash_lld_write(uint32_t startAddress, uint32_t length, const uint8_t* buffe
                 // Data synchronous Barrier, forcing the CPU to respect the sequence of instruction without optimization
                 __DSB();
 #endif                
+
+                // update flash pointer by the 'extra' byte that was programmed
+                cursor += 2;
             }
 
             // wait 500ms for any flash operation to be completed
@@ -218,7 +221,7 @@ int flash_lld_write(uint32_t startAddress, uint32_t length, const uint8_t* buffe
         }
 
         // after the program operation is completed disable the PG Bit
-        CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+        FLASH->CR &= (~FLASH_CR_PG);
 
         // lock the FLASH
         HAL_FLASH_Lock();

diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2/flash_lld.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2/flash_lld.h
@@ -48,6 +48,22 @@ typedef struct SMT32FlashDriver {
 #define FLASH_KEY2                  ((uint32_t)0xCDEF89ABU)
 #define SECTOR_MASK                 ((uint32_t)0xFFFFFF07)
 
+// FLASH_Error_Code FLASH Error Code
+#define HAL_FLASH_ERROR_NONE         ((uint32_t)0x00000000U)    /*!< No error                      */
+#define HAL_FLASH_ERROR_ERS          ((uint32_t)0x00000002U)    /*!< Programming Sequence error    */
+#define HAL_FLASH_ERROR_PGP          ((uint32_t)0x00000004U)    /*!< Programming Parallelism error */
+#define HAL_FLASH_ERROR_PGA          ((uint32_t)0x00000008U)    /*!< Programming Alignment error   */
+#define HAL_FLASH_ERROR_WRP          ((uint32_t)0x00000010U)    /*!< Write protection error        */
+#define HAL_FLASH_ERROR_OPERATION    ((uint32_t)0x00000020U)    /*!< Operation Error               */
+#define HAL_FLASH_ERROR_RD           ((uint32_t)0x00000040U)    /*!< Read Protection Error         */
+
+// FLASH_Program_Parallelism FLASH Program Parallelism
+#define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000U)
+#define FLASH_PSIZE_HALF_WORD      ((uint32_t)0x00000100U)
+#define FLASH_PSIZE_WORD           ((uint32_t)0x00000200U)
+#define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)0x00000300U)
+#define CR_PSIZE_MASK              ((uint32_t)0xFFFFFCFFU)
+
 //---------------------------------- STM32F4xx ------------------------------//
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
     defined(STM32F469xx) || defined(STM32F479xx) ||\
@@ -103,13 +119,6 @@ typedef struct SMT32FlashDriver {
 
 #endif
 
-// FLASH_Program_Parallelism FLASH Program Parallelism
-#define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000U)
-#define FLASH_PSIZE_HALF_WORD      ((uint32_t)0x00000100U)
-#define FLASH_PSIZE_WORD           ((uint32_t)0x00000200U)
-#define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)0x00000300U)
-#define CR_PSIZE_MASK              ((uint32_t)0xFFFFFCFFU)
-
 #define __HAL_FLASH_GET_FLAG(__FLAG__)   ((FLASH->SR & (__FLAG__)))
 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   (FLASH->SR = (__FLAG__))
 

diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv3/flash_lld.c b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv3/flash_lld.c
@@ -149,16 +149,19 @@ int flash_lld_write(uint32_t startAddress, uint32_t length, const uint8_t* buffe
                 // NOTE: assuming that the supply voltage is able to cope with half-word programming
                 if((endAddress - cursor) >= 2)
                 {
-                    *((__IO uint16_t*)cursor++) = *((uint16_t*)buffer++);
+                    *(__IO uint16_t*)cursor = *((uint16_t*)buffer);
 
                     // update flash and buffer pointers by the 'extra' byte that was programmed
-                    cursor++;
-                    buffer++;
+                    cursor += 2;
+                    buffer += 2;
                 }
                 else
                 {
                     // program single byte
-                    *((__IO uint8_t*)cursor++) = *((uint8_t*)buffer);
+                    *(__IO uint8_t*)cursor = *buffer;
+
+                    // update flash pointer by the 'extra' byte that was programmed
+                    cursor += 2;
                 }
             }
         }