Modeling-of-4-bit-Flash-ADC-and-4-bit-DAC

This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 4-bit ADC based on the flash architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.

Ideal Comparator

Ideal Clocked Comparator

4-bit Flash ADC

1- To create the Thermometer-Code Output, ((2^4)-1) Comparators & (2^4) voltage levels created by the resistive ladder are used. 2- To Convert the Thermometer-Code to a Binary-Code Output, a ROM Encoder is placed after the Comparators. 3- The whole flash ADC:

4-bit DAC

System Testbench

-> Using VerilogA blocks:

---

To analyze the output results:

• Using Cadence:
  Select the transient signal of the DAC's output, then use the "dft" & "dB20" functions in the ADE calculator to plot the output FFT spectrum.
  https://drive.google.com/open?id=1P0Qo3bQ7QQucbzPnD_u01404rpjmt8zj
  
• Using Matlab:
  Sample the transient signal of the DAC's output by using the "sample" function in the ADE calculator, then save tha samples in a CSV file, then Run the Matlab code on the CSV data.
  https://drive.google.com/file/d/1yapHM566FUtoERnFrU_xc2nd3FOF-ETe/view
  

---

References:

My project on google drive:
https://drive.google.com/drive/folders/1W9ip4MpMZNf3IQsoFQkhgg6QaUya4Yp4
EE288 Lecture Notes:
https://drive.google.com/drive/folders/12Qqfw_TX1i7dvVVYXksaSdHV4gth1OD5
Videos on how to create VerilogA blocks for ADCs: https://drive.google.com/drive/folders/1GAobRzzFTkD6ywqSdDJUsO5g2C06hh_i
https://www.youtube.com/channel/UC7jwESeWKLcRbtxHwFS3A7Q/videos