Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Miscellaneous fixes and improvements #1114

Merged
merged 12 commits into from
Jan 4, 2024
Merged
12 changes: 11 additions & 1 deletion src/modm/platform/adc/stm32f3/adc.hpp.in
Original file line number Diff line number Diff line change
Expand Up @@ -163,16 +163,22 @@ public:
// ADCs clock source selection
enum class ClockSource : uint32_t
{
NoClock = 0, // No clock selected.
%% if target["family"] in ["g4"]
NoClock = 0, // No clock selected.
%% if id in [1, 2]
Pll = RCC_{{ ccipr }}_ADC12SEL_0, // PLL “P” clock selected as ADC clock
SystemClock = RCC_{{ ccipr }}_ADC12SEL_1 , // System clock selected as ADCs clock
%% elif id in [3, 4, 5]
Pll = RCC_{{ ccipr }}_ADC345SEL_0, // PLL “P” clock selected as ADC clock
SystemClock = RCC_{{ ccipr }}_ADC345SEL_1 , // System clock selected as ADCs clock
%% endif
%% elif target["family"] in ["h7"]
Pll2P = 0,
Pll3R = RCC_{{ ccipr }}_ADCSEL_0,
PerClk = RCC_{{ ccipr }}_ADCSEL_1,
NoClock = PerClk, // for compatibility if sync. clock is used and setting is ignored
%% else
NoClock = 0, // No clock selected.
PllSai1 = RCC_{{ ccipr }}_ADCSEL_0, // PLLSAI1 "R" clock (PLLADC1CLK) selected as ADCs clock
%% if target["family"] != "l5"
PllSai2 = RCC_{{ ccipr }}_ADCSEL_1, // PLLSAI2 "R" clock (PLLADC2CLK) selected as ADCs clock
Expand Down Expand Up @@ -337,7 +343,11 @@ public:
static inline void
initialize( const ClockMode clk = ClockMode::DoNotChange,
%% if clock_mux
%% if target["family"] == "h7"
const ClockSource clk_src = ClockSource::PerClk,
%% else
const ClockSource clk_src = ClockSource::SystemClock,
%% endif
%% endif
const Prescaler pre = Prescaler::Disabled,
const CalibrationMode cal = CalibrationMode::DoNotCalibrate,
Expand Down
4 changes: 2 additions & 2 deletions src/modm/platform/adc/stm32f3/adc_impl.hpp.in
Original file line number Diff line number Diff line change
Expand Up @@ -195,14 +195,14 @@ modm::platform::Adc{{ id }}::configureChannel(Channel channel,
uint32_t tmpreg = 0;
if (static_cast<uint8_t>(channel) < 10) {
tmpreg = ADC{{ id }}->SMPR1
& ((~ADC_SMPR1_SMP0) << (static_cast<uint8_t>(channel) * 3));
& ~((ADC_SMPR1_SMP0) << (static_cast<uint8_t>(channel) * 3));
tmpreg |= static_cast<uint32_t>(sampleTime) <<
(static_cast<uint8_t>(channel) * 3);
ADC{{ id }}->SMPR1 = tmpreg;
}
else {
tmpreg = ADC{{ id }}->SMPR2
& ((~ADC_SMPR2_SMP10) << ((static_cast<uint8_t>(channel)-10) * 3));
& ~((ADC_SMPR2_SMP10) << ((static_cast<uint8_t>(channel)-10) * 3));
tmpreg |= static_cast<uint32_t>(sampleTime) <<
((static_cast<uint8_t>(channel)-10) * 3);
ADC{{ id }}->SMPR2 = tmpreg;
Expand Down
7 changes: 7 additions & 0 deletions src/modm/platform/clock/stm32/module.lb
Original file line number Diff line number Diff line change
Expand Up @@ -155,6 +155,13 @@ def build(env):
if "Fdcan1" in all_peripherals and per == "FDCAN":
per = "FDCAN1"
nper = "FDCAN"
# COMP12
if "Comp1" in all_peripherals and per == "COMP12":
per = "COMP1"
nper = "COMP12"
if "Comp2" in all_peripherals and per == "COMP12":
per = "COMP2"
nper = "COMP12"
# DAC
if "Dac1" in all_peripherals and per == "DAC":
per = "DAC1"
Expand Down
6 changes: 3 additions & 3 deletions src/modm/platform/dma/stm32/dma.hpp.in
Original file line number Diff line number Diff line change
Expand Up @@ -73,7 +73,7 @@ public:
%% endif
}
%% endif
%% if dmaType in ["stm32-mux"]:
%% if dmaType in ["stm32-mux"] and target.family != "g0":
Rcc::enable<Peripheral::Dmamux1>();
%% endif
}
Expand Down Expand Up @@ -295,7 +295,7 @@ public:
%% endif
})->muxChannel;
auto* channel = DMAMUX1_Channel0 + muxChannel;
channel->CCR = (channel->CCR & DMAMUX_CxCR_DMAREQ_ID) | uint32_t(dmaRequest);
channel->CCR = (channel->CCR & ~DMAMUX_CxCR_DMAREQ_ID) | uint32_t(dmaRequest);
%% elif dmaType in ["stm32-stream-channel"]
DMA_Channel_TypeDef *Channel = reinterpret_cast<DMA_Channel_TypeDef*>(CHANNEL_BASE);
Channel->CR = (Channel->CR & ~DMA_SxCR_CHSEL_Msk) | uint32_t(dmaRequest);
Expand Down Expand Up @@ -384,7 +384,7 @@ public:
static void
clearInterruptFlags(InterruptFlags_t flags = InterruptFlags::All)
{
ControlHal::clearInterruptFlags(flags, ChannelID);
ControlHal::clearInterruptFlags(InterruptFlags(flags.value), ChannelID);
}

/**
Expand Down
6 changes: 6 additions & 0 deletions src/modm/platform/timer/stm32/advanced.hpp.in
Original file line number Diff line number Diff line change
Expand Up @@ -255,6 +255,12 @@ public:
TIM{{ id }}->BDTR &= ~(TIM_BDTR_MOE);
}

static inline bool
isOutputEnabled()
{
return (TIM{{ id }}->BDTR & TIM_BDTR_MOE);
}

/*
* Enable/Disable automatic set of MOE bit at the next update event
*/
Expand Down
10 changes: 8 additions & 2 deletions src/modm/platform/timer/stm32/general_purpose.hpp.in
Original file line number Diff line number Diff line change
Expand Up @@ -110,8 +110,8 @@ public:
};

// This type is the internal size of the counter.
%% if id in [2, 5] and (target["family"] in ["f2", "f3", "f4", "f7", "l1", "l4", "g4"])
// Timer 2 and 5 are the only one which have the size of 32 bit
%% if id in [2, 5, 23, 24] and (target["family"] in ["f2", "f3", "f4", "f7", "l1", "l4", "g4", "h7"])
// Timer 2, 5, 23 and 24 are the only ones which have a 32 bit counter
using Value = uint32_t;

%% else
Expand Down Expand Up @@ -289,6 +289,12 @@ public:
TIM{{ id }}->BDTR &= ~(TIM_BDTR_MOE);
}

static inline bool
isOutputEnabled()
{
return (TIM{{ id }}->BDTR & TIM_BDTR_MOE);
}

/*
* Enable/Disable automatic set of MOE bit at the next update event
*/
Expand Down
2 changes: 2 additions & 0 deletions tools/build_script_generator/common.py
Original file line number Diff line number Diff line change
Expand Up @@ -213,6 +213,7 @@ def common_compiler_flags(compiler, target):
"-Werror=maybe-uninitialized",
"-Werror=overflow",
"-Werror=sign-compare",
"-Werror=return-type",
salkinium marked this conversation as resolved.
Show resolved Hide resolved
"-Wextra",
"-Wlogical-op",
"-Wpointer-arith",
Expand Down Expand Up @@ -274,6 +275,7 @@ def common_compiler_flags(compiler, target):
# "-Wold-style-cast",
"-fstrict-enums",
"-std=c++23",
"-Wno-psabi",
"-Wno-volatile", # volatile is deprecated in C++20 but lots of our external code uses it...
# "-pedantic",
]
Expand Down
2 changes: 1 addition & 1 deletion tools/build_script_generator/module.lb
Original file line number Diff line number Diff line change
Expand Up @@ -257,7 +257,7 @@ def post_build(env):
has_rtt = env.has_module(":platform:rtt")
env.substitutions["has_rtt"] = has_rtt
if has_rtt:
env.substitutions["main_ram"] = linkerscript.get("cont_ram_regions", [{"start": 0x20000000, "size": 4096}])[0]
env.substitutions["main_ram"] = linkerscript.get("cont_ram", {"start": 0x20000000, "size": 4096})
env.substitutions["rtt_channels"] = len(env.get(":platform:rtt:buffer.tx", []))
env.template("openocd.cfg.in")

Expand Down
2 changes: 1 addition & 1 deletion tools/modm_tools/unit_test.py
Original file line number Diff line number Diff line change
Expand Up @@ -91,7 +91,7 @@ def extract_tests(headers):
name = name[0]

functions = re.findall(
r"void\s+(test[A-Z]\w*)\s*\([\svoid]*\)\s*;", content)
r"void\s+(test[_a-zA-Z]\w*)\s*\([\svoid]*\)\s*;", content)
if not functions:
print("No tests found in {}!".format(header))

Expand Down
Loading