fixup: add documentation

src/modm/platform/core/stm32/module.lb

@@ -25,7 +25,7 @@ def prepare(module, options):
         module.add_option(
             EnumerationOption(
                 name="vector_table_location",
-                description="TODO", #FileReader("option/vector_table_location.md"),
+                description=FileReader("option/vector_table_location.md"),
                 enumeration=["rom", "ram"],
                 default="rom")
             )

src/modm/platform/core/stm32/module.md

@@ -440,3 +440,67 @@ placed into the 128kB DTCM, but cannot overflow into D1_SRAM section.
     ITCM    │  .vector_ram           │
 0x0000 0000 └────────────────────────┘◄ __itcm_start
 ```
+
+## Static RAM (SRAM) with vector table remap on F0 devices
+
+This memory map is identical to the SRAM default one, except that
+`.vector_ram` is placed at the beginning of SRAM1. It is used on STM32F0
+devices in case the platform-specific vector table relocation option
+`modm:platform:core:vector_table_location` is set to `ram`.
+
+```
+            ┌────────────────────────┐◄ __sram3_end
+            │ (+HEAP_SRAM3)          │
+            │ (.noinit_sram3)        │
+            │ (.bss_sram3)           │  only if SRAM3 exists
+   SRAM3    │ (.data_sram3)          │
+0x2003 0000 ├────────────────────────┤◄ __sram2_end, __sram3_start
+            │ (+HEAP_SRAM2)          │
+            │ (.noinit_sram2)        │
+            │ (.bss_sram2)           │  only if SRAM2 exists
+   SRAM2    │ (.data_sram2)          │
+0x2002 0000 ├────────────────────────┤◄ __sram1_end, __sram2_start
+            │  +HEAP_SRAM1           │
+            │  .noinit_sram1         │
+            │  .noinit               │
+            │  .faststack            │
+            │  .bss_sram1            │
+            │  .bss                  │
+            │  .data_sram1           │
+            │  .data                 │
+            │  .fastdata             │
+            │  .fastcode             │
+            │  +MAIN_STACK_SIZE      │◄ __main_stack_top
+   SRAM1    │  .vector_ram           │
+0x2000 0000 └────────────────────────┘◄ __sram1_start
+
+            ┌────────────────────────┐◄ __flash_end
+            │        (unused)        │
+            ├────────────────────────┤◄ __rom_end
+            │  .table.heap           │
+            │  .table.copy.extern    │
+   tables   │  .table.zero.extern    │
+            │  .table.copy.intern    │
+            │  .table.zero.intern    │
+            │                        │
+            │ (.data_sram3)          │◄ only if SRAM3 exists
+            │ (.data_sram2)          │◄ only if SRAM2 exists
+    copy    │  .data_sram1           │
+    only    │  .data                 │
+            │  .fastcode             │
+            │  .fastdata             │
+            │                        │
+            │  .note.gnu.build-id    │
+            │  .assertion            │
+            │  .hardware_init        │
+            │ (.eh_frame)            │
+    read    │ (.ARM.exidx)           │  only with C++ exceptions enabled
+    only    │ (.ARM.extab)           │
+            │  .init_array           │
+            │  .init                 │
+            │  .rodata               │
+            │  .text                 │
+   FLASH    │  .vector_rom           │
+0x0800 0000 └────────────────────────┘◄ __rom_start, __flash_start
+
+```

src/modm/platform/core/stm32/option/vector_table_location.md

@@ -0,0 +1,26 @@
+# Vector table location in ROM or RAM on F0 devices
+
+STM32 devices with a Cortex-M0 core provide a platform-specific method to place
+the interrupt vector table in SRAM although the core does not support vector
+table relocation. It is only available on STM32F0 since all other devices
+can remap the vector table in the Cortex-M core.
+
+When this method is activated the vector table is copied to the start of SRAM1
+by the startup script. The `SYSCFG->CFGR1` register is set to remap the
+beginning of SRAM to the vector table location at `0x0000 0000`.
+
+You can modify the RAM vector table using the CMSIS NVIC functions:
+
+- `void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)`
+- `uint32_t NVIC_GetVector(IRQn_Type IRQn)`
+
+This remapping method allows to easily boot an application from a custom
+bootloader even if the Cortex-M0 core does not support relocation.
+
+For applications that do not modify the vector table at runtime, relocation to
+RAM is not necessary and can save a few hundred bytes of static memory.
+
+!!! warning "On Interrupt Latency"
+    Placing main stack and vector table into the same memory can significantly
+    slow down interrupt latency, since both I-Code and D-Code memory interface
+    need to fetch from the same access port.