[gclk] Create a separate type for ClockPeripherals

modm-io · Jul 16, 2020 · e7d9846 · e7d9846
1 parent 8c27940
commit e7d9846
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Showing 5 changed files with 53 additions and 13 deletions.
diff --git a/src/modm/platform/clock/sam/gclk.hpp b/src/modm/platform/clock/sam/gclk.hpp
@@ -35,6 +35,50 @@ ClockGenerator : uint32_t
 	Internal8M = 3,
 };
 
+enum class ClockPeripheral : uint32_t {
+	Dfll48 = GCLK_CLKCTRL_ID_DFLL48_Val,
+	Fdpll = GCLK_CLKCTRL_ID_FDPLL_Val,
+	Fdpll32K = GCLK_CLKCTRL_ID_FDPLL32K_Val,
+	Wdt = GCLK_CLKCTRL_ID_WDT_Val,
+	Rtc = GCLK_CLKCTRL_ID_RTC_Val,
+	Eic = GCLK_CLKCTRL_ID_EIC_Val,
+	Usb = GCLK_CLKCTRL_ID_USB_Val,
+	Evsys0 = GCLK_CLKCTRL_ID_EVSYS_0_Val,
+	Evsys1 = GCLK_CLKCTRL_ID_EVSYS_1_Val,
+	Evsys2 = GCLK_CLKCTRL_ID_EVSYS_2_Val,
+	Evsys3 = GCLK_CLKCTRL_ID_EVSYS_3_Val,
+	Evsys4 = GCLK_CLKCTRL_ID_EVSYS_4_Val,
+	Evsys5 = GCLK_CLKCTRL_ID_EVSYS_5_Val,
+	Evsys6 = GCLK_CLKCTRL_ID_EVSYS_6_Val,
+	Evsys7 = GCLK_CLKCTRL_ID_EVSYS_7_Val,
+	Evsys8 = GCLK_CLKCTRL_ID_EVSYS_8_Val,
+	Evsys9 = GCLK_CLKCTRL_ID_EVSYS_9_Val,
+	Evsys10 = GCLK_CLKCTRL_ID_EVSYS_10_Val,
+	Evsys11 = GCLK_CLKCTRL_ID_EVSYS_11_Val,
+	SercomXSlow = GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val,
+	Sercom0 = GCLK_CLKCTRL_ID_SERCOM0_CORE_Val,
+	Sercom1 = GCLK_CLKCTRL_ID_SERCOM1_CORE_Val,
+	Sercom2 = GCLK_CLKCTRL_ID_SERCOM2_CORE_Val,
+	Sercom3 = GCLK_CLKCTRL_ID_SERCOM3_CORE_Val,
+	Sercom4 = GCLK_CLKCTRL_ID_SERCOM4_CORE_Val,
+	Sercom5 = GCLK_CLKCTRL_ID_SERCOM5_CORE_Val,
+	Tcc0 = GCLK_CLKCTRL_ID_TCC0_TCC1_Val,
+	Tcc1 = GCLK_CLKCTRL_ID_TCC0_TCC1_Val,
+	Tcc2 = GCLK_CLKCTRL_ID_TCC2_TC3_Val,
+	Tc3 = GCLK_CLKCTRL_ID_TCC2_TC3_Val,
+	Tc4 = GCLK_CLKCTRL_ID_TC4_TC5_Val,
+	Tc5 = GCLK_CLKCTRL_ID_TC4_TC5_Val,
+	Tc6 = GCLK_CLKCTRL_ID_TC6_TC7_Val,
+	Tc7 = GCLK_CLKCTRL_ID_TC6_TC7_Val,
+	Adc = GCLK_CLKCTRL_ID_ADC_Val,
+	AcDig = GCLK_CLKCTRL_ID_AC_DIG_Val,
+	AcAna = GCLK_CLKCTRL_ID_AC_ANA_Val,
+	Dac = GCLK_CLKCTRL_ID_DAC_Val,
+	Ptc = GCLK_CLKCTRL_ID_PTC_Val,
+	I2s0 = GCLK_CLKCTRL_ID_I2S_0_Val,
+	I2s1 = GCLK_CLKCTRL_ID_I2S_1_Val
+};
+
 /**
  * Clock management
  *
@@ -65,9 +109,9 @@ class GenericClockController
 		ClockSource source = ClockSource::OSC8M,
 		uint32_t waitCycles = 2048);
 
-	template< Peripheral peripheral >
+	template< ClockPeripheral peripheral >
 	static void
-	enable(ClockGenerator clockGen);
+	connect(ClockGenerator clockGen);
 
 private:
 

diff --git a/src/modm/platform/clock/sam/gclk_impl.hpp.in b/src/modm/platform/clock/sam/gclk_impl.hpp.in
@@ -41,16 +41,14 @@ GenericClockController::setFlashLatency()
 	return Core_Hz;
 }
 
-	template< Peripheral peripheral >
+	template< ClockPeripheral peripheral >
 	void
-	GenericClockController::enable(ClockGenerator clockGen)
+	GenericClockController::connect(ClockGenerator clockGen)
 	{
-		if constexpr (peripheral == Peripheral::Eic) {
-			GCLK->CLKCTRL.reg =
+		GCLK->CLKCTRL.reg =
 				GCLK_CLKCTRL_CLKEN |
 				GCLK_CLKCTRL_GEN(uint32_t(clockGen)) |
-				GCLK_CLKCTRL_ID_EIC;
-		}
+				GCLK_CLKCTRL_ID(uint32_t(peripheral));
 	}
 
 }

diff --git a/src/modm/platform/extint/sam/extint.cpp b/src/modm/platform/extint/sam/extint.cpp
@@ -25,7 +25,7 @@ ExternalInterrupt::initialize(ClockGenerator clockGen, int priority) {
 	NVIC_SetPriority(EIC_IRQn, priority);
 	NVIC_EnableIRQ(EIC_IRQn);
 
-	GenericClockController::enable<Peripheral::Eic>(clockGen);
+	GenericClockController::connect<ClockPeripheral::Eic>(clockGen);
 
 	// Enable EIC
 	EIC->CTRL.bit.ENABLE = 1;

diff --git a/src/modm/platform/uart/sam/uart_hal.hpp.in b/src/modm/platform/uart/sam/uart_hal.hpp.in
@@ -17,6 +17,7 @@
 #include <stdint.h>
 #include "../device.hpp"
 #include "uart_base.hpp"
+#include "modm/platform/clock/gclk.hpp"
 #include "modm/platform/core/peripherals.hpp"
 
 namespace modm

diff --git a/src/modm/platform/uart/sam/uart_hal_impl.hpp.in b/src/modm/platform/uart/sam/uart_hal_impl.hpp.in
@@ -58,10 +58,7 @@ modm::platform::{{ name }}::initialize(Parity parity)
 {
 	// Enable peripheral clock in power manager.
 	PM->APBCMASK.bit.{{ peripheral }}_ = true;
-	// Init clock using GCLK0 as source.
-	GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_{{ peripheral }}_CORE |
-                      GCLK_CLKCTRL_GEN_GCLK0 |
-                      GCLK_CLKCTRL_CLKEN ;
+	GenericClockController::connect<ClockPeripheral::{{ sercom }}>(ClockGenerator::System);
 	while (GCLK->STATUS.bit.SYNCBUSY);
 	// Reset USART
 	reset();