DMA for STM32F4/F7, still not working...

modm-io · Oct 24, 2021 · b0857fd · b0857fd
1 parent 36969b1
commit b0857fd
Show file tree

Hide file tree

Showing 2 changed files with 45 additions and 58 deletions.
diff --git a/README.md b/README.md
@@ -208,8 +208,8 @@ Please [discover modm's peripheral drivers for your specific device][discover].
 <td align="center">✅</td>
 <td align="center">○</td>
 <td align="center">✅</td>
-<td align="center">○</td>
-<td align="center">○</td>
+<td align="center">✅</td>
+<td align="center">✅</td>
 <td align="center">✅</td>
 <td align="center">✅</td>
 <td align="center">○</td>

diff --git a/src/modm/platform/dma/stm32/dma_base.hpp.in b/src/modm/platform/dma/stm32/dma_base.hpp.in
@@ -51,57 +51,44 @@ public:
 	enum class
 	Channel
 	{
-		Channel0 = 0,
-		Channel1,
-		Channel2,
-		Channel3,
-		Channel4,
-		Channel5,
-		Channel6,
-		Channel7,
+		Stream0 = 0,
+		Stream1,
+		Stream2,
+		Stream3,
+		Stream4,
+		Stream5,
+		Stream6,
+		Stream7,
+		Channel0 = Stream0,
+		Channel1 = Stream1,
+		Channel2 = Stream2,
+		Channel3 = Stream3,
+		Channel4 = Stream4,
+		Channel5 = Stream5,
+		Channel6 = Stream6,
+		Channel7 = Stream7,
 	};
 
-	enum class
-	Request : uint32_t
-	{
-		Channel0 = 0,
-		Channel1 = DMA_SxCR_CHSEL_0,
-		Channel2 = DMA_SxCR_CHSEL_1,
-		Channel3 = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0,
-		Channel4 = DMA_SxCR_CHSEL_2,
-		Channel5 = DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0,
-		Channel6 = DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1,
-		Channel7 = DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0,
-	};
-
-	/*
-	enum class
-	MemoryBurstTransfer : uint32_t
-	{
-		Single 		= 0,
-		Increment4 	= DMA_SxCR_MBURST_0,
-		Increment8 	= DMA_SxCR_MBURST_1,
-		Increment16 = DMA_SxCR_MBURST_1 | DMA_SxCR_MBURST_0,
-	};
-
-	enum class
-	PeripheralBurstTransfer : uint32_t
-	{
-		Single 		= 0,
-		Increment4 	= DMA_SxCR_PBURST_0,
-		Increment8 	= DMA_SxCR_PBURST_1,
-		Increment16 = DMA_SxCR_PBURST_1 | DMA_SxCR_PBURST_0,
-	};
+	%% set request_count = namespace(max_requests = 0)
+	%% for streams in dma["channels"]
+		%% for stream in streams.stream
+			%% for channel in stream.channel
+				%% if request_count.max_requests < channel.position | int
+					%% set request_count.max_requests = channel.position | int
+				%% endif
+			%% endfor
+		%% endfor
+	%% endfor
 
 	enum class
-	FlowControl : uint32_t
+	Request : uint32_t
 	{
-		Dma 		= 0,
-		Peripheral 	= DMA_SxCR_PFCTRL, ///< the peripheral is the flow controller
+	%% for i in range(0, request_count.max_requests + 1)
+		Channel{{ i }} = ({{ i }} << DMA_SxCR_CHSEL_Pos),
+	%% endfor
 	};
-	*/
 
-%% elif dmaType in ["stm32-channel-request", "stm32-channel", "stm32-mux"]
+%% elif dmaType in ["stm32-channel-request", "stm32-channel", "stm32-mux", "stm32-stream-channel"]
 	enum class
 	Channel
 	{
@@ -258,20 +245,20 @@ public:
 protected:
 %% if dmaType in ["stm32-stream-channel"]
 	static constexpr uint32_t memoryMask =
-			DMA_SxCR_MBURST_1 | DMA_SxCR_MBURST_0 |	// MemoryBurstTransfer
-			DMA_SxCR_MSIZE_0  | DMA_SxCR_MSIZE_1  |	// MemoryDataSize
-			DMA_SxCR_MINC                         |	// MemoryIncrementMode
-			DMA_SxCR_DIR_0    | DMA_SxCR_DIR_1;    	// DataTransferDirection
+			DMA_SxCR_MBURST_Msk |					// MemoryBurstTransfer
+			DMA_SxCR_MSIZE_Msk |					// MemoryDataSize
+			DMA_SxCR_MINC |							// MemoryIncrementMode
+			DMA_SxCR_DIR_Msk;    					// DataTransferDirection
 	static constexpr uint32_t peripheralMask =
-			DMA_SxCR_PBURST_1 | DMA_SxCR_PBURST_0 |	// PeripheralBurstTransfer
-			DMA_SxCR_PSIZE_0  | DMA_SxCR_PSIZE_1  |	// PeripheralDataSize
-			DMA_SxCR_PINC                         |	// PeripheralIncrementMode
-			DMA_SxCR_DIR_0    | DMA_SxCR_DIR_1;    	// DataTransferDirection
+			DMA_SxCR_PBURST_Msk |					// PeripheralBurstTransfer
+			DMA_SxCR_PSIZE_Msk |					// PeripheralDataSize
+			DMA_SxCR_PINC_Msk |						// PeripheralIncrementMode
+			DMA_SxCR_DIR_Msk;						// DataTransferDirection
 	static constexpr uint32_t configmask =
-			DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0 |	// Channel
-			DMA_SxCR_PL_1    | DMA_SxCR_PL_0    |						// Priority
-			DMA_SxCR_CIRC    |											// CircularMode
-			DMA_SxCR_PFCTRL;											// FlowControl
+			DMA_SxCR_CHSEL_Msk |					// Channel
+			DMA_SxCR_PL_Msk |						// Priority
+			DMA_SxCR_CIRC_Msk |						// CircularMode
+			DMA_SxCR_PFCTRL_Msk;					// FlowControl
 %% elif dmaType in ["stm32-channel-request", "stm32-channel", "stm32-mux"]
 	static constexpr uint32_t memoryMask =
 			DMA_CCR_MSIZE_0  | DMA_CCR_MSIZE_1  |	// MemoryDataSize