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[stm32] Fix linkerscript veneer offset issues
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@salkinium
salkinium committed Oct 23, 2021
1 parent 82bc4a9 commit 1b41daf
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Showing 5 changed files with 21 additions and 26 deletions.
24 changes: 12 additions & 12 deletions src/modm/platform/core/cortex/linker.macros
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Original file line number Diff line number Diff line change
Expand Up @@ -91,18 +91,13 @@ TOTAL_STACK_SIZE = MAIN_STACK_SIZE + PROCESS_STACK_SIZE;
{
. = ALIGN(4);
__table_zero_intern_start = .;
LONG(__bss_start)
LONG(__bss_end)
%% for name in zero
LONG(__{{name}}_start)
LONG(__{{name}}_end)
%% endfor
__table_zero_intern_end = .;

__table_copy_intern_start = .;
LONG(__data_load)
LONG(__data_start)
LONG(__data_end)
%% for name in copy
LONG(__{{name}}_load)
LONG(__{{name}}_start)
Expand Down Expand Up @@ -143,26 +138,29 @@ TOTAL_STACK_SIZE = MAIN_STACK_SIZE + PROCESS_STACK_SIZE;
} >{{memory}}
%% endmacro

%% macro section(memory, name, sections=[])
%% macro section(memory, name, table_copy, sections=[])
%% do table_copy.append(name)
.{{name}} :
{
. = ALIGN(4);
__{{name}}_load = LOADADDR(.{{name}});
__{{name}}_start = .;
*(.{{name}} .{{name}}.*)
. = ALIGN(4);
__{{name}}_end = .;
} >{{memory}}

%% do table_copy.extend(sections)
%% for section in sections
.{{section}} :
{
__{{section}}_load = LOADADDR(.{{section}});
__{{section}}_start = .;
*(.{{section}} .{{section}}.*)
. = ALIGN(4);
__{{section}}_end = .;
} >{{memory}}
%% endfor
__{{name}}_end = .;
%% endmacro


Expand Down Expand Up @@ -192,8 +190,7 @@ TOTAL_STACK_SIZE = MAIN_STACK_SIZE + PROCESS_STACK_SIZE;
%% for cont_region in cont_ram_regions
%% for region in cont_region.contains
%% if region.index
{{ section(cont_region.name|upper + " AT >FLASH", "data_"+region.name) }}
%% do table_copy.append("data_"+region.name)
{{ section(cont_region.name|upper + " AT >FLASH", "data_"+region.name, table_copy) }}
%% do table_zero.append("bss_"+region.name)
%% endif

Expand Down Expand Up @@ -280,16 +277,19 @@ TOTAL_STACK_SIZE = MAIN_STACK_SIZE + PROCESS_STACK_SIZE;
%% endmacro


%% macro section_ram(memory, rom, sections_data=[], sections_bss=[])
%% macro section_ram(memory, rom, table_copy, table_zero, sections_data=[], sections_bss=[])
%% do table_copy.append("data")
.data :
{
. = ALIGN(4);
__data_load = LOADADDR(.data);
__data_start = .;
*(.data .data.* .gnu.linkonce.d.*)
. = ALIGN(4);
__data_end = .;
} >{{memory}} AT >{{rom}}

%% do table_copy.extend(sections_data)
%% for section in sections_data
.{{section}} :
{
Expand All @@ -300,8 +300,8 @@ TOTAL_STACK_SIZE = MAIN_STACK_SIZE + PROCESS_STACK_SIZE;
__{{section}}_end = .;
} >{{memory}} AT >{{rom}}
%% endfor
__data_end = .;

%% do table_zero.append("bss")
.bss (NOLOAD) :
{
__bss_start = . ;
Expand All @@ -310,6 +310,7 @@ TOTAL_STACK_SIZE = MAIN_STACK_SIZE + PROCESS_STACK_SIZE;
__bss_end = .;
} >{{memory}}

%% do table_zero.extend(sections_bss)
%% for section in sections_bss
.{{section}} (NOLOAD) :
{
Expand All @@ -319,7 +320,6 @@ TOTAL_STACK_SIZE = MAIN_STACK_SIZE + PROCESS_STACK_SIZE;
__{{section}}_end = .;
} >{{memory}}
%% endfor
__bss_end = .;

.noinit (NOLOAD) :
{
Expand Down
2 changes: 1 addition & 1 deletion src/modm/platform/core/cortex/ram.ld.in
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ SECTIONS
{{ linker.section_vector_ram(cont_ram_regions[0].name|upper) }}
%% endif

{{ linker.section_ram(cont_ram_regions[0].name|upper, "FLASH",
{{ linker.section_ram(cont_ram_regions[0].name|upper, "FLASH", table_copy, table_zero,
sections_data=["fastdata", "fastcode", "data_" + cont_ram_regions[0].contains[0].name],
sections_bss=["bss_" + cont_ram_regions[0].contains[0].name]) }}

Expand Down
8 changes: 3 additions & 5 deletions src/modm/platform/core/stm32/dccm.ld.in
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Original file line number Diff line number Diff line change
Expand Up @@ -20,16 +20,15 @@ SECTIONS
{{ linker.section_vector_ram(cont_ram_regions[0].name|upper) }}
%% endif

{{ linker.section_ram(cont_ram_regions[0].name|upper, "FLASH",
{{ linker.section_ram(cont_ram_regions[0].name|upper, "FLASH", table_copy, table_zero,
sections_data=["fastcode", "data_" + cont_ram_regions[0].contains[0].name],
sections_bss=["bss_" + cont_ram_regions[0].contains[0].name]) }}

{{ linker.all_heap_sections(table_copy, table_zero, table_heap) }}


%% if "backup" in regions
{{ linker.section("BACKUP AT >FLASH", "data_backup") }}
%% do table_copy.append("data_backup")
{{ linker.section("BACKUP AT >FLASH", "data_backup", table_copy) }}

{{ linker.section_heap("BACKUP", "heap_backup", sections=["bss_backup", "noinit_backup"]) }}
%% do table_heap.append({"name": "heap_backup", "prop": "0x4009"})
Expand All @@ -40,8 +39,7 @@ SECTIONS
{{ linker.section_stack("CCM") }}

/* CCM can only be accessed by D-Bus, do not place .fastcode here! */
{{ linker.section("CCM AT >FLASH", "fastdata", sections=["data_ccm"]) }}
%% do table_copy.append("fastdata")
{{ linker.section("CCM AT >FLASH", "fastdata", table_copy, sections=["data_ccm"]) }}

{{ linker.section_heap("CCM", "heap_ccm", sections=["bss_ccm", "noinit_ccm"]) }}
%% do table_heap.append({"name": "heap_ccm", "prop": "0x2002"})
Expand Down
5 changes: 2 additions & 3 deletions src/modm/platform/core/stm32/iccm.ld.in
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ SECTIONS

{{ linker.section_stack(cont_ram_regions[0].name|upper) }}

{{ linker.section_ram(cont_ram_regions[0].name|upper, "FLASH",
{{ linker.section_ram(cont_ram_regions[0].name|upper, "FLASH", table_copy, table_zero,
sections_data=["data_" + cont_ram_regions[0].contains[0].name],
sections_bss=["bss_" + cont_ram_regions[0].contains[0].name]) }}

Expand All @@ -32,8 +32,7 @@ SECTIONS
{{ linker.section_vector_ram("CCM") }}
%% endif

{{ linker.section("CCM AT >FLASH", "fastcode", sections=["fastdata", "data_ccm"]) }}
%% do table_copy.append("fastcode")
{{ linker.section("CCM AT >FLASH", "fastcode", table_copy, sections=["fastdata", "data_ccm"]) }}

{{ linker.section_heap("CCM", "heap_ccm", sections=["bss_ccm", "noinit_ccm"]) }}
%% do table_heap.append({"name": "heap_ccm", "prop": "0x2006"})
Expand Down
8 changes: 3 additions & 5 deletions src/modm/platform/core/stm32/idtcm.ld.in
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Original file line number Diff line number Diff line change
Expand Up @@ -20,16 +20,15 @@ SECTIONS
{{ linker.section_vector_ram("ITCM") }}
%% endif

{{ linker.section("ITCM AT >FLASH", "fastcode", sections=["data_itcm"]) }}
%% do table_copy.append("fastcode")
{{ linker.section("ITCM AT >FLASH", "fastcode", table_copy, sections=["data_itcm"]) }}

{{ linker.section_heap("ITCM", "heap_itcm", sections=["noinit_itcm"]) }}
%% do table_heap.append({"name": "heap_itcm", "prop": "0x201f"})


{{ linker.section_stack("CONT_DTCM") }}

{{ linker.section_ram(cont_ram_regions[0].name|upper, "FLASH",
{{ linker.section_ram(cont_ram_regions[0].name|upper, "FLASH", table_copy, table_zero,
sections_data=["fastdata", "data_" + cont_ram_regions[0].contains[0].name],
sections_bss=["bss_" + cont_ram_regions[0].contains[0].name]) }}

Expand All @@ -40,8 +39,7 @@ SECTIONS


%% if "backup" in regions
{{ linker.section("BACKUP AT >FLASH", "data_backup") }}
%% do table_copy.append("data_backup")
{{ linker.section("BACKUP AT >FLASH", "data_backup", table_copy) }}

{{ linker.section_heap("BACKUP", "heap_backup", sections=["bss_backup", "noinit_backup"]) }}
%% do table_heap.append({"name": "heap_backup", "prop": "0x4009"})
Expand Down

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