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Enable static CPU offload for FP16/BF16 CUDA MoE #33039
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f587392
Enable static CPU offload for FP16 CUDA MoE
xadupre 94d0479
Merge origin/main into moe-fp16-static-cpu-offload
xadupre e224f2d
Use CPU expert count for MoE offload
xadupre 418f028
Address static MoE offload review feedback
xadupre 47ddc99
Address static MoE offload review feedback
xadupre d4103d8
Fix cross-platform MoE build errors
Copilot 6d293cd
Overlap MoE CPU input transfer with routing
xadupre 75e917c
Fix MoE all-CPU offload preparation
xadupre ee7c675
Keep offloaded MoE initializers on CPU
xadupre 61f587a
Address MoE offload review findings
xadupre a2c8d4b
Refine MoE CPU offload execution
xadupre 10b24f7
Test mixed MoE expert contributions
xadupre 9d97a2f
Address final MoE offload review
xadupre 6a9d27a
Merge remote-tracking branch 'origin/main' into moe-fp16-static-cpu-o…
xadupre 59b5940
Fix MoE CPU offload build and execution
xadupre 61b8a25
Address remaining MoE offload review findings
xadupre 212c47c
Fix MoE offload CI regressions
xadupre f212726
Handle legacy MoE weight layouts in CPU offload
xadupre 02e7c69
Fix ARM Python image dependency installation
xadupre 4813edd
Address remaining MoE offload review concerns
xadupre 9792f1a
Complete MoE offload retention, coverage and documentation fixes
xadupre de41b65
Cover all FP16 CPU offload activations and SwiGLU parameters
xadupre 1ac39a6
Fix mixed MoE offload input aliasing race
xadupre b4ef8fc
Test MoE CPU offload prepacking requirement
xadupre 7bb43c5
Respect subgraph scope in MoE offload initializer validation
xadupre 66fc23b
Scope MoE expert initializer collection to actual captures
xadupre 6c57615
Test sparse mixer rejection with MoE CPU offload
xadupre 56f08e8
Verify non-square MoE layouts against CUDA-only execution
xadupre b45f46e
Add BF16 CUDA MoE CPU offload
xadupre 46bbd97
Exclude BF16 MoE bridge from minimal builds
xadupre 6553fd8
Address BF16 MoE offload review feedback
xadupre 951bede
Exclude MoE offload plumbing from minimal builds
xadupre 2eb7d63
Remove MoE offload handling from minimal builds
xadupre da0162a
Merge remote-tracking branch 'origin/main' into moe-fp16-static-cpu-o…
Copilot 2834ef3
Fix MoE offload review regressions
xadupre ef78678
Fix MoE profiling branch selection
xadupre 07bb1cd
Keep minimal MoE validation compact
xadupre a805b04
Fix CUDA MoE offload device handling
xadupre 0f4eebc
Simplify MoE expert counter decay
xadupre c482daf
Fix alpha-only counter log expectation
xadupre f008ad4
Update MoE counters on CUDA and compact CPU offload work
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We seldom use fp16/bf16 MoE for CUDA EP, since most models need quantize to int4/nvfp4 QMoE operator for performance and VRAM limit.
This PR adds a feature that might not be used.
We shall focus on make a real use case like qwen 3.8 flash next model with int4 or nvfp4 QMoE that run end-to-end with onnxruntime-genai integration.
There are a few things need consideration:
(1) CPU and CUDA kernel shall use same prepacked format, so that we need not transform the data layout after we copy expert weights from CPU to GPU.
(2) ORT and GenAI integration: we might let GenAI handle some expert weights copy or take part in planning.
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I started with this one to simplify the transfer between CUDA/CPU. I know it has to be extended to QMoE but the kernels has different prepacking so the transfer is not straightforward. My first goal is agree on a design valid for both first.