webgpu: Optimize DP4A SmallM MatMulNBits tiling#27910
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Change default DP4A SmallM tile parameters from tile_size_k_vec=16, tile_size_n=32 to tile_size_k_vec=32, tile_size_n=4, increasing K-parallelism (32 threads along K vs 16) at the cost of fewer concurrent B rows (4 vs 32). This was previously Intel-only and is now the default for all vendors. On Qualcomm, improving token generation from ~20 tps to ~25 tps. Changes: - dp4a_matmul_nbits.cc: Default tile params to k_vec=32, tile_n=4; remove Intel-specific override (now redundant).
guschmue
approved these changes
Mar 31, 2026
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This pull request adjusts the tiling strategy for small matrix sizes in the DP4A matmul kernel. The changes are aimed at improving performance and compatibility, especially for specific GPU vendors.
On Qualcomm, improving token generation from ~20 tps to ~25 tps.