Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Build the x86 STL with /arch:SSE2 instead of /arch:IA32 #4741

Merged
merged 3 commits into from
Jun 21, 2024
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 0 additions & 1 deletion CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,6 @@ if("${VCLIBS_TARGET_ARCHITECTURE}" STREQUAL "x86")
# Note that we set _WIN32_WINNT to a high level to make declarations available, but still engage downlevel
# runtime dynamic linking by setting our own _STL_WIN32_WINNT back to Windows XP.
add_compile_definitions(_X86_ _VCRT_WIN32_WINNT=0x0501 _STL_WIN32_WINNT=0x0501)
add_compile_options($<$<COMPILE_LANGUAGE:CXX>:/arch:IA32>)
elseif(VCLIBS_TARGET_ARCHITECTURE STREQUAL "x64")
set(VCLIBS_TARGET_ARCHITECTURE "x64")
set(VCLIBS_I386_OR_AMD64 "amd64")
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -65,10 +65,6 @@ int main() {
disable_instructions(__ISA_AVAILABLE_SSE42);
test_all_element_sizes(p, page);
#endif // defined(_M_IX86) || defined(_M_X64)
#if defined(_M_IX86)
disable_instructions(__ISA_AVAILABLE_SSE2);
test_all_element_sizes(p, page);
#endif // defined(_M_IX86)

VirtualFree(p, 0, MEM_RELEASE);
}
6 changes: 0 additions & 6 deletions tests/std/tests/VSO_0000000_vector_algorithms/test.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1180,11 +1180,5 @@ int main() {
test_various_containers();
test_bitset(gen);
#endif // defined(_M_IX86) || defined(_M_X64)
#if defined(_M_IX86)
disable_instructions(__ISA_AVAILABLE_SSE2);
test_vector_algorithms(gen);
test_various_containers();
test_bitset(gen);
#endif // defined(_M_IX86)
#endif // _M_CEE_PURE
}
1 change: 0 additions & 1 deletion tests/std/tests/floating_point_model_matrix.lst
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@ RUNALL_CROSSLIST
* PM_CL="/FIfenv_prefix.hpp /w14640 /Zc:threadSafeInit- /EHsc /std:c++latest"
RUNALL_CROSSLIST
* PM_CL=""
* PM_CL="/arch:IA32"
* PM_CL="/arch:AVX2"
* PM_CL="/arch:VFPv4"
RUNALL_CROSSLIST
Expand Down
1 change: 0 additions & 1 deletion tests/utils/stl/test/features.py
Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,6 @@ def getDefaultFeatures(config, litConfig):
DEFAULT_FEATURES.append(Feature(name='edg_drop'))

if litConfig.target_arch.casefold() == 'x86'.casefold():
DEFAULT_FEATURES.append(Feature(name='arch_ia32'))
DEFAULT_FEATURES.append(Feature(name='arch_avx2'))
DEFAULT_FEATURES.append(Feature(name='x86'))

Expand Down
2 changes: 0 additions & 2 deletions tests/utils/stl/test/tests.py
Original file line number Diff line number Diff line change
Expand Up @@ -290,8 +290,6 @@ def _parseFlags(self, litConfig):
self.requires.append('edg') # available for x64, see features.py
elif flag[1:] == 'arch:AVX2':
self.requires.append('arch_avx2') # available for x86 and x64, see features.py
elif flag[1:] == 'arch:IA32':
self.requires.append('arch_ia32') # available for x86, see features.py
elif flag[1:] == 'arch:VFPv4':
self.requires.append('arch_vfpv4') # available for arm, see features.py
elif flag[1:] == 'MDd':
Expand Down