[IR] Add llvm.masked.{udiv,sdiv,urem,srem} intrinsics

[lukel97]

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[Copilot]

Pull request overview

This PR introduces new masked integer division and remainder intrinsics (llvm.masked.{udiv,sdiv,urem,srem}) and wires them through SelectionDAG so targets can legalize/expand them, with backend coverage via new CodeGen tests.

Changes:

• Add IR intrinsics and LangRef documentation for masked integer div/rem that produce poison on disabled lanes (and avoid div-by-zero UB on disabled lanes).
• Add new SelectionDAG opcodes (ISD::MASKED_{U,S}{DIV,REM}) plus builder/dumper support.
• Implement core legalization/expansion paths for the new masked operations and add AArch64/RISCV/PowerPC CodeGen tests.

Reviewed changes

Copilot reviewed 32 out of 32 changed files in this pull request and generated 1 comment.

Show a summary per file

File	Description
llvm/include/llvm/IR/Intrinsics.td	Defines the new llvm.masked.{u,s}{div,rem} intrinsics.
llvm/docs/LangRef.rst	Documents semantics and signatures for the new intrinsics.
llvm/include/llvm/CodeGen/ISDOpcodes.h	Adds new ISD::MASKED_* opcodes and helper declaration.
llvm/include/llvm/Target/TargetSelectionDAG.td	Adds SDNode/type profile definitions for the masked div/rem nodes.
llvm/lib/CodeGen/TargetLoweringBase.cpp	Sets default operation action for masked div/rem to Expand.
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp	Lowers the new intrinsics to the new ISD::MASKED_* nodes.
llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp	Adds textual names for new ISD::MASKED_* nodes.
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Adds ISD::getUnmaskedBinOpOpcode() mapping masked→unmasked opcode.
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp	Adds expansion support for masked div/rem during vector op legalization.
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp	Adds scalarize/split/widen handling for the new masked nodes.
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h	Declares new legalization helper methods for masked div/rem.
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp	Adds integer promotion handling for masked div/rem and their mask operands.
llvm/test/CodeGen/RISCV/rvv/masked-udiv.ll	New RVV CodeGen checks for llvm.masked.udiv.
llvm/test/CodeGen/RISCV/rvv/masked-sdiv.ll	New RVV CodeGen checks for llvm.masked.sdiv.
llvm/test/CodeGen/RISCV/rvv/masked-urem.ll	New RVV CodeGen checks for llvm.masked.urem.
llvm/test/CodeGen/RISCV/rvv/masked-srem.ll	New RVV CodeGen checks for llvm.masked.srem.
llvm/test/CodeGen/PowerPC/masked-udiv.ll	New PowerPC CodeGen checks for llvm.masked.udiv.
llvm/test/CodeGen/PowerPC/masked-sdiv.ll	New PowerPC CodeGen checks for llvm.masked.sdiv.
llvm/test/CodeGen/PowerPC/masked-urem.ll	New PowerPC CodeGen checks for llvm.masked.urem.
llvm/test/CodeGen/PowerPC/masked-srem.ll	New PowerPC CodeGen checks for llvm.masked.srem.
llvm/test/CodeGen/AArch64/masked-udiv-scalable.ll	New SVE CodeGen checks for masked unsigned division (scalable vectors).
llvm/test/CodeGen/AArch64/masked-sdiv-scalable.ll	New SVE CodeGen checks for masked signed division (scalable vectors).
llvm/test/CodeGen/AArch64/masked-urem-scalable.ll	New SVE CodeGen checks for masked unsigned remainder (scalable vectors).
llvm/test/CodeGen/AArch64/masked-srem-scalable.ll	New SVE CodeGen checks for masked signed remainder (scalable vectors).
llvm/test/CodeGen/AArch64/masked-udiv-fixed-length.ll	New NEON/SVE CodeGen checks for masked unsigned division (fixed-length vectors).

[Copilot]

This new LangRef section uses British spelling ("undefined behaviour"), but the rest of LangRef consistently uses "undefined behavior". Please switch to "behavior" here (and in the other sentences in this section) for consistency.