[regfile_fpga] oh_raddr_*_err signals unassigned if RdataMuxCheck=0

[glaserf]

Observed Behavior

The onehot-error signals in relation to the read addresses (oh_raddr_a_err, oh_raddr_b_err) in rtl/ibex_register_file_fpga.sv are unassigned for non-secure Ibex configurations (which is for example used for opentitan FPGA top-levels IIRC):

ibex/rtl/ibex_register_file_fpga.sv

Lines 152 to 158 in 667fd20

	end else begin : gen_no_rdata_mux_check
	// async_read a
	assign rdata_a_o = (raddr_a_i == '0) ? WordZeroVal : mem[raddr_a_i];
	// async_read b
	assign rdata_b_o = (raddr_b_i == '0) ? WordZeroVal : mem[raddr_b_i];
	end

This leads to the regfile err_o signal becoming x

ibex/rtl/ibex_register_file_fpga.sv

Line 55 in 667fd20

assign err_o = oh_raddr_a_err || oh_raddr_b_err || oh_we_err;

which triggers assertions (at least for us) when simulating with the FPGA regfile. It however seems to not cause issues during synthesis, at least with Vivado.

I am also unsure about the comments that refer to rdata_*_o as asynchronous:

ibex/rtl/ibex_register_file_fpga.sv

Lines 153 to 154 in 667fd20

	// async_read a
	assign rdata_a_o = (raddr_a_i == '0) ? WordZeroVal : mem[raddr_a_i];

Expected Behavior

Same as for the other regfile variants; signals in question being tied to 1'b0 for RdataMuxCheck = 0.

[shareefj]

See #2241

[rswarbrick]

Oh! Looks like it's fixed! Thanks for adding a note.

About the asynchronous comments, they date back to the original version of the file (from 2020). I think the author probably meant to point out that raddr_a_i feeds through to rdata_a_o without any register stage, so isn't synchronous to some clock. But it's rather confusingly phrased.

I've just checked, and the behaviour is the same for e.g. ibex_register_file_ff. I'll file a PR to drop the comment for the FPGA register file so that things are a bit less confusing.