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[PowerPC] Respect endianness when bitcasting to fp128 #95931

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Aug 8, 2024
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[PowerPC] Respect endianness when bitcasting to fp128 #95931

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14 changes: 9 additions & 5 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -9361,14 +9361,18 @@ SDValue PPCTargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
SDLoc dl(Op);
SDValue Op0 = Op->getOperand(0);

SDValue Lo = Op0.getOperand(0);
SDValue Hi = Op0.getOperand(1);

if ((Op.getValueType() != MVT::f128) ||
(Op0.getOpcode() != ISD::BUILD_PAIR) ||
(Op0.getOperand(0).getValueType() != MVT::i64) ||
(Op0.getOperand(1).getValueType() != MVT::i64) || !Subtarget.isPPC64())
(Op0.getOpcode() != ISD::BUILD_PAIR) || (Lo.getValueType() != MVT::i64) ||
(Hi.getValueType() != MVT::i64) || !Subtarget.isPPC64())
return SDValue();

return DAG.getNode(PPCISD::BUILD_FP128, dl, MVT::f128, Op0.getOperand(0),
Op0.getOperand(1));
if (!Subtarget.isLittleEndian())
std::swap(Lo, Hi);

return DAG.getNode(PPCISD::BUILD_FP128, dl, MVT::f128, Lo, Hi);
}

static const SDValue *getNormalLoadInput(const SDValue &Op, bool &IsPermuted) {
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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/PowerPC/f128-aggregates.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -283,7 +283,7 @@ define fp128 @testMixedAggregate([3 x i128] %a.coerce) {
;
; CHECK-BE-LABEL: testMixedAggregate:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrdd v2, r8, r7
; CHECK-BE-NEXT: mtvsrdd v2, r7, r8
; CHECK-BE-NEXT: blr
;
; CHECK-P8-LABEL: testMixedAggregate:
Expand All @@ -310,7 +310,7 @@ define fp128 @testMixedAggregate_02([4 x i128] %a.coerce) {
;
; CHECK-BE-LABEL: testMixedAggregate_02:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrdd v2, r6, r5
; CHECK-BE-NEXT: mtvsrdd v2, r5, r6
; CHECK-BE-NEXT: blr
;
; CHECK-P8-LABEL: testMixedAggregate_02:
Expand Down Expand Up @@ -344,7 +344,7 @@ define fp128 @testMixedAggregate_03([4 x i128] %sa.coerce) {
; CHECK-BE-LABEL: testMixedAggregate_03:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrwa v2, r4
; CHECK-BE-NEXT: mtvsrdd v3, r6, r5
; CHECK-BE-NEXT: mtvsrdd v3, r5, r6
; CHECK-BE-NEXT: xscvsdqp v2, v2
; CHECK-BE-NEXT: xsaddqp v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r9
Expand Down Expand Up @@ -467,7 +467,7 @@ define fp128 @testUnion_01([1 x i128] %a.coerce) {
;
; CHECK-BE-LABEL: testUnion_01:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrdd v2, r4, r3
; CHECK-BE-NEXT: mtvsrdd v2, r3, r4
; CHECK-BE-NEXT: blr
;
; CHECK-P8-LABEL: testUnion_01:
Expand All @@ -494,7 +494,7 @@ define fp128 @testUnion_02([1 x i128] %a.coerce) {
;
; CHECK-BE-LABEL: testUnion_02:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrdd v2, r4, r3
; CHECK-BE-NEXT: mtvsrdd v2, r3, r4
; CHECK-BE-NEXT: blr
;
; CHECK-P8-LABEL: testUnion_02:
Expand All @@ -521,7 +521,7 @@ define fp128 @testUnion_03([4 x i128] %a.coerce) {
;
; CHECK-BE-LABEL: testUnion_03:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrdd v2, r8, r7
; CHECK-BE-NEXT: mtvsrdd v2, r7, r8
; CHECK-BE-NEXT: blr
;
; CHECK-P8-LABEL: testUnion_03:
Expand Down
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