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[llvm][CodeGen] Fix failure in window scheduler caused by weak dependencies #95636

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Merged
dtcxzyw merged 2 commits into from
Jun 15, 2024
Merged

[llvm][CodeGen] Fix failure in window scheduler caused by weak dependencies #95636

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9f9f068
[llvm][CodeGen] Fix failure in window scheduler caused by weak depend…
huaatian Jun 15, 2024
98fd0d9
[llvm][CodeGen] Modifications made based on review comments 1
huaatian Jun 15, 2024
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4 changes: 3 additions & 1 deletion llvm/lib/CodeGen/WindowScheduler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -422,6 +422,8 @@ int WindowScheduler::calculateMaxCycle(ScheduleDAGInstrs &DAG,
int ExpectCycle = CurCycle;
// The predecessors of current MI determine its earliest issue cycle.
for (auto &Pred : SU->Preds) {
if (Pred.isWeak())
continue;
auto *PredMI = Pred.getSUnit()->getInstr();
int PredCycle = getOriCycle(PredMI);
ExpectCycle = std::max(ExpectCycle, PredCycle + (int)Pred.getLatency());
Expand Down Expand Up @@ -479,7 +481,7 @@ int WindowScheduler::calculateStallCycle(unsigned Offset, int MaxCycle) {
auto *SU = TripleDAG->getSUnit(&MI);
int DefCycle = getOriCycle(&MI);
for (auto &Succ : SU->Succs) {
if (Succ.getSUnit() == &TripleDAG->ExitSU)
if (Succ.isWeak() || Succ.getSUnit() == &TripleDAG->ExitSU)
continue;
// If the expected cycle does not exceed MaxCycle, no check is needed.
if (DefCycle + (int)Succ.getLatency() <= MaxCycle)
Expand Down
39 changes: 39 additions & 0 deletions llvm/test/CodeGen/Hexagon/swp-ws-weak-dep.mir
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@@ -0,0 +1,39 @@
# REQUIRES: asserts
# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
# RUN: -window-sched=force -filetype=null 2>&1 | FileCheck %s

# CHECK: SU(3): Ord Latency=0 Weak
# CHECK: SU(1): Ord Latency=0 Weak
# CHECK: Window scheduling is not needed!

---
name: khazad_setkey_in_key
tracksRegLiveness: true
body: |
bb.0:
successors: %bb.1(0x80000000)
liveins: $r0, $r1

%0:intregs = COPY $r1
%1:intregs = COPY $r0
J2_loop0i %bb.1, 1, implicit-def $lc0, implicit-def $sa0, implicit-def $usr

bb.1:
successors: %bb.2(0x04000000), %bb.1(0x7c000000)

%2:doubleregs = L2_loadrd_io %1, 0
%3:intregs = COPY %2.isub_lo
S2_storeri_io %0, 0, %3
%4:intregs = S2_asl_i_r %2.isub_hi, 2
%5:intregs = L2_loadri_io %4, 0
%6:intregs = S4_andi_asl_ri 4, %3, 1
%7:intregs = L2_loadri_io %6, 0
%8:intregs = A2_xor %7, %5
S2_storeri_io %1, 0, %8
ENDLOOP0 %bb.1, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
J2_jump %bb.2, implicit-def dead $pc

bb.2:
PS_jmpret $r31, implicit-def dead $pc

...