Commits on Jun 5, 2024

1. [LSR][AArch64] Optimize chain generation based on legal addressing mo… …

   …des.
   
   LSR will generate chains of related instructions with a known increment between
   them. With SVE, in the case of the test case, this can include increments like
   'vscale * 16 + 8'.  The idea of this patch is if we have a '+8' increment
   already calculated in the chain, we can generate a (legal) '+ vscale*16'
   addressing mode from it, allowing us to use the '[x16, llvm#1, mul vl]' addressing
   mode instructions.
   
   In order to do this we keep track of the known 'bases' when generating chains
   in GenerateIVChain, checking for each if the accumulated increment expression
   neatly folds into a legal addressing mode. If they do not we fall back to the
   existing LeftOverExpr, whether it is legal or not.
   
   This is mostly orthogonal to llvm#88124, dealing with the generation of chains as
   opposed to rest of LSR. The existing vscale addressing mode work has greatly
   helped compared to the last time I looked at this, allowing us to check that
   the addressing modes are indeed legal.

   

   davemgreen committed Jun 5, 2024
   Configuration menu

   • View commit details
   • Copy full SHA for 826e30d
   • Browse repository at this point

   Copy the full SHA

   826e30d View commit details

   Browse the repository at this point in the history