Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

[PowerPC] Add the SCV instruction. #68063

Merged
merged 1 commit into from
Oct 5, 2023
Merged

[PowerPC] Add the SCV instruction. #68063

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
5 changes: 3 additions & 2 deletions llvm/lib/Target/PowerPC/PPCInstrFormats.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -220,7 +220,7 @@ BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
}

// 1.7.3 SC-Form
class SCForm<bits<6> opcode, bits<1> xo,
class SCForm<bits<6> opcode, bits<1> xo1, bits<1> xo2,
dag OOL, dag IOL, string asmstr, InstrItinClass itin,
list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> {
Expand All @@ -229,7 +229,8 @@ class SCForm<bits<6> opcode, bits<1> xo,
let Pattern = pattern;

let Inst{20-26} = LEV;
let Inst{30} = xo;
let Inst{30} = xo1;
let Inst{31} = xo2;
}

// 1.7.4 D-Form
Expand Down
10 changes: 9 additions & 1 deletion llvm/lib/Target/PowerPC/PPCInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1641,10 +1641,18 @@ let isBranch = 1, isTerminator = 1, Size = 0 in {

// System call.
let PPC970_Unit = 7 in {
def SC : SCForm<17, 1, (outs), (ins i32imm:$LEV),
def SC : SCForm<17, 1, 0, (outs), (ins i32imm:$LEV),
"sc $LEV", IIC_BrB, [(PPCsc (i32 imm:$LEV))]>;
}

// We mark SCV as having no scheduling model since it is only meant to be used
// as inline assembly. If we implement a builtin pattern for it we will need to
// add it to the P9 and P10 scheduling models.
let Predicates = [IsISA3_0], hasNoSchedulingInfo = 1 in {
def SCV : SCForm<17, 0, 1, (outs), (ins i32imm:$LEV),
"scv $LEV", IIC_BrB, []>;
}

// Branch history rolling buffer.
def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB,
[(PPCclrbhrb)]>,
Expand Down
6 changes: 6 additions & 0 deletions llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -73,6 +73,12 @@
# CHECK: sc
0x44 0x00 0x00 0x02

# CHECK: scv 1
0x44 0x00 0x00 0x21

# CHECK: scv 2
0x44 0x00 0x00 0x41

# CHECK: clrbhrb
0x7c 0x00 0x03 0x5c

Expand Down
6 changes: 6 additions & 0 deletions llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -73,6 +73,12 @@
# CHECK: sc
0x02 0x00 0x00 0x44

# CHECK: scv 1
0x21 0x00 0x00 0x44

# CHECK: scv 2
0x41 0x00 0x00 0x44

# CHECK: clrbhrb
0x5c 0x03 0x00 0x7c

Expand Down
9 changes: 8 additions & 1 deletion llvm/test/MC/PowerPC/ppc64-encoding.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -144,7 +144,7 @@
# CHECK-LE: mcrf 2, 3 # encoding: [0x00,0x00,0x0c,0x4d]
mcrf 2, 3

# System call instruction
# System call instructions

# CHECK-BE: sc 1 # encoding: [0x44,0x00,0x00,0x22]
# CHECK-LE: sc 1 # encoding: [0x22,0x00,0x00,0x44]
Expand All @@ -153,6 +153,13 @@
# CHECK-LE: sc # encoding: [0x02,0x00,0x00,0x44]
sc

# CHECK-BE: scv 1 # encoding: [0x44,0x00,0x00,0x21]
# CHECK-LE: scv 1 # encoding: [0x21,0x00,0x00,0x44]
scv 1
# CHECK-BE: scv 2 # encoding: [0x44,0x00,0x00,0x41]
# CHECK-LE: scv 2 # encoding: [0x41,0x00,0x00,0x44]
scv 2

# Branch history rolling buffer

# CHECK-BE: clrbhrb # encoding: [0x7c,0x00,0x03,0x5c]
Expand Down