Skip to content

[RISCV] Avoid forming Zilsd pairs with x0 for non-x0 register classes #211019

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
svs-quic merged 2 commits into from
Jul 22, 2026
+44 −1
Merged

[RISCV] Avoid forming Zilsd pairs with x0 for non-x0 register classes #211019

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
4ade2fd
Pre-commit test
svs-quic Jul 21, 2026
2814f2f
[RISCV] Check Vreg Register Class before allowing x0_pair
svs-quic Jul 21, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 2 additions & 1 deletion llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -223,7 +223,8 @@ bool RISCVPreAllocZilsdOpt::canFormLdSdPair(MachineInstr *MI0,
if (FirstReg == SecondReg) {
const MachineInstr *FirstOpDefInst = MRI->getUniqueVRegDef(FirstReg);
if (FirstOpDefInst->isCopy() &&
FirstOpDefInst->getOperand(1).getReg() == RISCV::X0)
FirstOpDefInst->getOperand(1).getReg() == RISCV::X0 &&
Comment thread
svs-quic marked this conversation as resolved.
MRI->getRegClass(FirstReg)->contains(RISCV::X0))
return true;
return false;
}
Expand Down
42 changes: 42 additions & 0 deletions llvm/test/CodeGen/RISCV/zilsd-ldst-opt-prera.mir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,13 @@
ret void
}

define void @basic_store_zero_no_combine(ptr %0, i32 %1, i32 %2) {
store i32 0, ptr %0, align 4
%4 = getelementptr inbounds i32, ptr %0, i32 1
store i32 0, ptr %4, align 4
ret void
}

define i32 @basic_load_combine_8_byte_aligned(ptr %0) {
%2 = load i32, ptr %0, align 8
%3 = getelementptr inbounds i32, ptr %0, i32 1
Expand Down Expand Up @@ -364,6 +371,41 @@ body: |
SW %1, %0, 4 :: (store (s32))
PseudoRET

...
---
# Basic case: two consecutive 32-bit store 0 that cannot be combined into SD
name: basic_store_zero_no_combine
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x10', virtual-reg: '%0' }
body: |
bb.0:
liveins: $x10

; CHECK-LABEL: name: basic_store_zero_no_combine
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x0
; CHECK-NEXT: SW [[COPY1]], [[COPY]], 0 :: (store (s32))
; CHECK-NEXT: SW [[COPY1]], [[COPY]], 4 :: (store (s32))
; CHECK-NEXT: PseudoRET
;
; CHECK-4BYTE-LABEL: name: basic_store_zero_no_combine
; CHECK-4BYTE: liveins: $x10
; CHECK-4BYTE-NEXT: {{ $}}
; CHECK-4BYTE-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-4BYTE-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x0
; CHECK-4BYTE-NEXT: SW [[COPY1]], [[COPY]], 0 :: (store (s32))
; CHECK-4BYTE-NEXT: SW [[COPY1]], [[COPY]], 4 :: (store (s32))
; CHECK-4BYTE-NEXT: PseudoRET
%0:gpr = COPY $x10
%1:gprnox0 = COPY $x0
SW %1, %0, 0 :: (store (s32))
SW %1, %0, 4 :: (store (s32))
PseudoRET

...
---
name: basic_load_combine_8_byte_aligned
Expand Down
Loading