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[VPlan] Fold lhs | (headermask && rhs) -> vp.merge rhs, true, lhs, evl #193511

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Merged
lukel97 merged 2 commits into from
Apr 24, 2026
Merged

[VPlan] Fold lhs | (headermask && rhs) -> vp.merge rhs, true, lhs, evl #193511

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[VPlan] Fold lhs | (headermask && rhs) -> vp.merge rhs, true, lhs, evl
lukel97 Apr 22, 2026
2e4bf03
Merge branch 'main' into loop-vectorize/optimizeMaskToEVL-logical-or
lukel97 Apr 24, 2026
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8 changes: 8 additions & 0 deletions llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3208,6 +3208,14 @@ static VPRecipeBase *optimizeMaskToEVL(VPValue *HeaderMask,
VPIRFlags::getDefaultFlags(Instruction::Sub), {}, DL);
}

// lhs | (headermask && rhs) -> vp.merge rhs, true, lhs, evl
if (match(&CurRecipe,
m_c_BinaryOr(m_VPValue(LHS),

@fhahn fhahn Apr 23, 2026

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There's probably no way to the the variant where LHS is on the right size, exercising the commutative match, right?

@lukel97 lukel97 Apr 24, 2026

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I'm not sure, I don't think VPlanPredicator will ever create a block-in mask with a header mask on only one arm of an or. This particular or comes from LoopVectorizationPlanner::addReductionResultComputation which always puts the header mask if any on the RHS.

m_LogicalAnd(m_Specific(HeaderMask), m_VPValue(RHS)))))
return new VPWidenIntrinsicRecipe(
Intrinsic::vp_merge, {RHS, Plan->getTrue(), LHS, &EVL},
TypeInfo.inferScalarType(LHS), {}, {}, DL);

return nullptr;
}

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3 changes: 1 addition & 2 deletions llvm/test/Transforms/LoopVectorize/RISCV/iv-select-cmp.ll
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Expand Up @@ -96,9 +96,8 @@ define i64 @select_decreasing_induction_icmp_non_const_start(ptr %a, ptr %b, i64
; CHECK-NEXT: [[VP_OP_LOAD4:%.*]] = call <vscale x 4 x i64> @llvm.vp.load.nxv4i64.p0(ptr align 8 [[TMP14]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP4]])
; CHECK-NEXT: [[TMP15:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vp.reverse.nxv4i64(<vscale x 4 x i64> [[VP_OP_LOAD4]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP4]])
; CHECK-NEXT: [[TMP16:%.*]] = icmp sgt <vscale x 4 x i64> [[TMP12]], [[TMP15]]
; CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 4 x i1> @llvm.vp.merge.nxv4i1(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x i1> [[TMP16]], <vscale x 4 x i1> zeroinitializer, i32 [[TMP4]])
; CHECK-NEXT: [[TMP18]] = call <vscale x 4 x i64> @llvm.vp.merge.nxv4i64(<vscale x 4 x i1> [[TMP16]], <vscale x 4 x i64> [[VEC_IND]], <vscale x 4 x i64> [[VEC_PHI]], i32 [[TMP4]])
; CHECK-NEXT: [[TMP19]] = or <vscale x 4 x i1> [[VEC_PHI1]], [[TMP17]]
; CHECK-NEXT: [[TMP19]] = call <vscale x 4 x i1> @llvm.vp.merge.nxv4i1(<vscale x 4 x i1> [[TMP16]], <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i1> [[VEC_PHI1]], i32 [[TMP4]])
; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add i64 [[TMP5]], [[INDEX]]
; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP5]]
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <vscale x 4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT3]]
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