Skip to content

[PowerPC] Add pnop (prefixed no-op) instruction (ISA v3.1) #188373

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
Scottcjn wants to merge 1 commit into
base: main
Choose a base branch
from
+32 −0
Open

[PowerPC] Add pnop (prefixed no-op) instruction (ISA v3.1) #188373

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
16 changes: 16 additions & 0 deletions llvm/lib/Target/PowerPC/PPCInstrP10.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2988,3 +2988,19 @@ let Predicates = [IsISA3_1, PrefixInstrs], isAsmParserOnly = 1, hasNoSchedulingI
(ins s34imm64_pcrel:$SI),
"pla $RT, $SI", IIC_IntSimple, []>, isPCRel;
}

// pnop - Prefixed No-Op (Power ISA v3.1, Section 3.3.1.2)
// Prefix word 0x07000000: primary opcode 1, prefix type 3, remaining bits 0.
// Suffix word 0x00000000. Like all prefixed instructions it must not cross a
// 64-byte boundary.
let Predicates = [PrefixInstrs],
hasNoSchedulingInfo = 1, hasSideEffects = 0,
mayLoad = 0, mayStore = 0 in {
def PNOP : PI<1, 0, (outs), (ins), "pnop", IIC_IntSimple> {
// Prefix: type 3, remaining prefix bits all zero.
let Inst{6...7} = 3;
let Inst{8...31} = 0;
// Suffix: bits 38-63 all zero (bits 32-37 already = 0 from opcode)
let Inst{38...63} = 0;
}
}
6 changes: 6 additions & 0 deletions llvm/test/MC/Disassembler/PowerPC/ppc-pnop.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,6 @@
# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-linux-gnu \
# RUN: -mcpu=pwr10 | FileCheck %s

# Prefixed no-op (Power ISA v3.1). Instruction bytes are big-endian.
# CHECK: pnop
0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00
10 changes: 10 additions & 0 deletions llvm/test/MC/PowerPC/ppc-pnop.s
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,10 @@
# RUN: llvm-mc -triple powerpc64-unknown-linux-gnu -show-encoding %s | \
# RUN: FileCheck %s --check-prefix=CHECK-BE
# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu -show-encoding %s | \
# RUN: FileCheck %s --check-prefix=CHECK-LE

# Prefixed no-op (Power ISA v3.1, Section 3.3.1.2)
# Encoding: prefix 0x0700_0000 + suffix 0x0000_0000
pnop
# CHECK-BE: pnop # encoding: [0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
# CHECK-LE: pnop # encoding: [0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x00]