[AlexVlx]

This adds a SPIR-V intrinsic for associating a name (textual identifier) to a specialisation constant. The name is encoded in metadata, and is intended to be used within LLVM / by the SPIR-V BE (e.g. #134016 would be a direct user), as it is never emitted into the SPIR-V object. Non-boolean and composite specialisation constants will be handled in the future, via dedicated intrinsics, if there is interest.

[llvmbot]

@llvm/pr-subscribers-backend-spir-v

Author: Alex Voicu (AlexVlx)

Changes

This adds a SPIR-V intrinsic for associating a name (textual identifier) to a specialisation constant. The name is encoded in metadata, and is intended to be used within LLVM / by the SPIR-V BE (e.g. #134016 would be a direct user), as it is never emitted into the SPIR-V object. Non-boolean and composite specialisation constants will be handled in the future, via dedicated intrinsics, if there is interest.

---

Full diff: https://github.com/llvm/llvm-project/pull/187420.diff

3 Files Affected:

• (modified) llvm/include/llvm/IR/IntrinsicsSPIRV.td (+5)
• (modified) llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp (+14)
• (modified) llvm/test/CodeGen/SPIRV/constant/spec-constant.ll (+20-1)

diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index 5d467adb08c3d..51cb430f4bd43 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -43,6 +43,11 @@ let TargetPrefix = "spv" in {
   def int_spv_alloca_array : Intrinsic<[llvm_any_ty], [llvm_anyint_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
   def int_spv_undef : Intrinsic<[llvm_i32_ty], []>;
   def int_spv_inline_asm : Intrinsic<[], [llvm_metadata_ty, llvm_metadata_ty, llvm_vararg_ty]>;
+  def int_spv_named_boolean_spec_constant
+      : Intrinsic<[llvm_i1_ty], [llvm_i32_ty, llvm_i1_ty, llvm_metadata_ty],
+                  [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
+  // TODO: possibly add intrinsics for other types of Spec Constants and a
+  //       corresponding Clang builtin.
 
   // Masked Gather/Scatter (SPV_INTEL_masked_gather_scatter)
   def int_spv_masked_gather : Intrinsic<[llvm_any_ty],
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index eb30002d2e1a5..c045ab693e9ab 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -4125,6 +4125,20 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
     MIB.constrainAllUses(TII, TRI, RBI);
     return true;
   }
+  case Intrinsic::spv_named_boolean_spec_constant: {
+    auto Opcode = I.getOperand(3).getImm()
+        ? SPIRV::OpSpecConstantTrue : SPIRV::OpSpecConstantFalse;
+
+    auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
+                   .addDef(I.getOperand(0).getReg())
+                   .addUse(GR.getSPIRVTypeID(ResType));
+    MIB.constrainAllUses(TII, TRI, RBI);
+    unsigned SpecId = I.getOperand(2).getImm();
+    buildOpDecorate(I.getOperand(0).getReg(), *MIB.getInstr(), TII,
+                    SPIRV::Decoration::SpecId, {SpecId});
+
+    return true;
+  }
   case Intrinsic::spv_const_composite: {
     // If no values are attached, the composite is null constant.
     bool IsNull = I.getNumExplicitDefs() + 1 == I.getNumExplicitOperands();
diff --git a/llvm/test/CodeGen/SPIRV/constant/spec-constant.ll b/llvm/test/CodeGen/SPIRV/constant/spec-constant.ll
index 299d61d3bffde..5ca7a504addf7 100644
--- a/llvm/test/CodeGen/SPIRV/constant/spec-constant.ll
+++ b/llvm/test/CodeGen/SPIRV/constant/spec-constant.ll
@@ -8,6 +8,8 @@
 ; CHECK-DAG: OpDecorate [[float_const:%[0-9]+]] SpecId 8
 ; CHECK-DAG: OpDecorate [[double_const:%[0-9]+]] SpecId 9
 ; CHECK-DAG: OpDecorate [[enum_const:%[0-9]+]] SpecId 10
+; CHECK-DAG: OpDecorate [[named_bool_const_true:%[0-9]+]] SpecId 11
+; CHECK-DAG: OpDecorate [[named_bool_const_false:%[0-9]+]] SpecId 12
 
 ; CHECK-DAG: [[bool_const]] = OpSpecConstantTrue {{%[0-9]+}}
 ; CHECK-DAG: [[short_const]] = OpSpecConstant {{%[0-9]+}} 4
@@ -16,6 +18,8 @@
 ; CHECK-DAG: [[float_const]] = OpSpecConstant {{%[0-9]+}} 1112014848
 ; CHECK-DAG: [[double_const]] = OpSpecConstant {{%[0-9]+}} 0 1079574528
 ; CHECK-DAG: [[enum_const]] = OpSpecConstant {{%[0-9]+}} 30
+; CHECK-DAG: [[named_bool_const_true:%[0-9]+]] = OpSpecConstantTrue {{%[0-9]+}}
+; CHECK-DAG: [[named_bool_const_false:%[0-9]+]] = OpSpecConstantFalse {{%[0-9]+}}
 
 @_ZL10bool_const = internal addrspace(10) global i32 0, align 4
 @_ZL11short_const = internal addrspace(10) global i16 0, align 2
@@ -58,6 +62,18 @@ entry:
   ; CHECK: OpStore {{%[0-9]+}} [[enum_const]]
   %18 = tail call spir_func i32 @_Z20__spirv_SpecConstantii(i32 10, i32 30)
   store i32 %18, ptr addrspace(10) @_ZL10enum_const, align 4
+
+  ; CHECK: [[bt:%[0-9]+]] = OpSelect {{%[0-9]+}} [[named_bool_const_true]]
+  ; CHECK: OpStore {{%[0-9]+}} [[bt]]
+  %19 = tail call spir_func i1 @llvm.spv.named.boolean.spec.constant(i32 11, i1 true, metadata !{})
+  %zext_0 = zext i1 %19 to i32
+  store i32 %zext_0, ptr addrspace(10) @_ZL10bool_const, align 4
+
+  ; CHECK: [[bf:%[0-9]+]] = OpSelect {{%[0-9]+}} [[named_bool_const_false]]
+  ; CHECK: OpStore {{%[0-9]+}} [[bf]]
+  %20 = tail call spir_func i1 @llvm.spv.named.boolean.spec.constant(i32 12, i1 false, metadata !{})
+  %zext_1 = zext i1 %20 to i32
+  store i32 %zext_1, ptr addrspace(10) @_ZL10bool_const, align 4
   ret void
 }
 
@@ -69,5 +85,8 @@ declare i32 @_Z20__spirv_SpecConstantii(i32, i32)
 declare i64 @_Z20__spirv_SpecConstantix(i32, i64)
 declare float @_Z20__spirv_SpecConstantif(i32, float)
 declare double @_Z20__spirv_SpecConstantid(i32, double)
+declare i1 @llvm.spv.named.boolean.spec.constant(i32, i1, metadata)
+
+attributes #0 = { "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" }
 
-attributes #0 = { "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" }
\ No newline at end of file
+!0 = !{ !"" }
\ No newline at end of file

[github-actions]

✅ With the latest revision this PR passed the C/C++ code formatter.

[MrSidims]

LGTM, just 1 Q