[PowerPC] Add bctar instruction (ISA 2.07) - #187322
Open
Scottcjn wants to merge 6 commits into
Open
Conversation
|
Thank you for submitting a Pull Request (PR) to the LLVM Project! This PR will be automatically labeled and the relevant teams will be notified. If you wish to, you can add reviewers by using the "Reviewers" section on this page. If this is not working for you, it is probably because you do not have write permissions for the repository. In which case you can instead tag reviewers by name in a comment by using If you have received no comments on your PR for a week, you can request a review by "ping"ing the PR by adding a comment “Ping”. The common courtesy "ping" rate is once a week. Please remember that you are asking for valuable time from other developers. If you have further questions, they may be answered by the LLVM GitHub User Guide. You can also ask questions in a comment on this PR, on the LLVM Discord or on the forums. |
Member
|
@llvm/pr-subscribers-backend-powerpc Author: AutoJanitor (Scottcjn) ChangesSummaryAdd assembly/disassembly support for
Fixes #176864 Test plan
Full diff: https://github.com/llvm/llvm-project/pull/187322.diff 2 Files Affected:
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 3271e4d279f56..0e8209bcb548c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1590,6 +1590,24 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
"bcctr 4, $BI, 0", IIC_BrB, []>;
}
}
+
+ // bctar - Branch Conditional to TAR (ISA 2.07 / POWER8)
+ let Predicates = [IsISA2_07] in {
+ let isBranch = 1, isIndirectBranch = 1 in {
+ let isCodeGenOnly = 1 in {
+ def BCCTAR : XLForm_2_br<19, 560, 0, (outs), (ins (pred $BIBO, $CR):$cond),
+ "b${cond:cc}tar${cond:pm} ${cond:reg}", IIC_BrB,
+ []>;
+ }
+ }
+ let isCall = 1, Defs = [LR] in {
+ let isCodeGenOnly = 1 in {
+ def BCCTARL : XLForm_2_br<19, 560, 1, (outs), (ins (pred $BIBO, $CR):$cond),
+ "b${cond:cc}tarl${cond:pm} ${cond:reg}", IIC_BrB,
+ []>;
+ }
+ }
+ }
}
// Set the float rounding mode.
@@ -5223,6 +5241,18 @@ let PPC970_Unit = 7, isBranch = 1, hasSideEffects = 0 in {
def gBCCTRL : XLForm_2<19, 528, 1, (outs),
(ins u5imm:$BO, crbitrc:$BI, i32imm:$BH),
"bcctrl $BO, $BI, $BH", IIC_BrB, []>;
+
+ // bctar/bctarl - Branch Conditional to TAR (ISA 2.07 / POWER8)
+ let Predicates = [IsISA2_07] in {
+ let Uses = [RM] in
+ def gBCTAR : XLForm_2<19, 560, 0, (outs),
+ (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH),
+ "bctar $BO, $BI, $BH", IIC_BrB, []>;
+ let Defs = [LR], Uses = [RM] in
+ def gBCTARL : XLForm_2<19, 560, 1, (outs),
+ (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH),
+ "bctarl $BO, $BI, $BH", IIC_BrB, []>;
+ }
}
multiclass BranchSimpleMnemonicAT<string pm, int at> {
@@ -5242,6 +5272,10 @@ def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
+let Predicates = [IsISA2_07] in {
+def : InstAlias<"bctar $bo, $bi", (gBCTAR u5imm:$bo, crbitrc:$bi, 0)>;
+def : InstAlias<"bctarl $bo, $bi", (gBCTARL u5imm:$bo, crbitrc:$bi, 0)>;
+}
multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
@@ -5256,17 +5290,40 @@ multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
}
-defm : BranchSimpleMnemonic2<"t", "", 12>;
-defm : BranchSimpleMnemonic2<"f", "", 4>;
-defm : BranchSimpleMnemonic2<"t", "-", 14>;
-defm : BranchSimpleMnemonic2<"f", "-", 6>;
-defm : BranchSimpleMnemonic2<"t", "+", 15>;
-defm : BranchSimpleMnemonic2<"f", "+", 7>;
+multiclass BranchSimpleMnemonic3<string name, string pm, int bo>
+ : BranchSimpleMnemonic2<name, pm, bo> {
+ let Predicates = [IsISA2_07] in {
+ def : InstAlias<"b"#name#"tar"#pm#" $bi", (gBCTAR bo, crbitrc:$bi, 0)>;
+ def : InstAlias<"b"#name#"tarl"#pm#" $bi", (gBCTARL bo, crbitrc:$bi, 0)>;
+ }
+}
+defm : BranchSimpleMnemonic3<"t", "", 12>;
+defm : BranchSimpleMnemonic3<"f", "", 4>;
+defm : BranchSimpleMnemonic3<"t", "-", 14>;
+defm : BranchSimpleMnemonic3<"f", "-", 6>;
+defm : BranchSimpleMnemonic3<"t", "+", 15>;
+defm : BranchSimpleMnemonic3<"f", "+", 7>;
defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
defm : BranchSimpleMnemonic1<"dzt", "", 10>;
defm : BranchSimpleMnemonic1<"dzf", "", 2>;
+// bdnztar/bdztar - Branch Decrement CTR to TAR (ISA 2.07)
+let Predicates = [IsISA2_07] in {
+def : InstAlias<"bdnztar", (gBCTAR 16, CR0LT, 0)>;
+def : InstAlias<"bdnztar+", (gBCTAR 25, CR0LT, 0)>;
+def : InstAlias<"bdnztar-", (gBCTAR 24, CR0LT, 0)>;
+def : InstAlias<"bdnztarl", (gBCTARL 16, CR0LT, 0)>;
+def : InstAlias<"bdnztarl+", (gBCTARL 25, CR0LT, 0)>;
+def : InstAlias<"bdnztarl-", (gBCTARL 24, CR0LT, 0)>;
+def : InstAlias<"bdztar", (gBCTAR 18, CR0LT, 0)>;
+def : InstAlias<"bdztar+", (gBCTAR 27, CR0LT, 0)>;
+def : InstAlias<"bdztar-", (gBCTAR 26, CR0LT, 0)>;
+def : InstAlias<"bdztarl", (gBCTARL 18, CR0LT, 0)>;
+def : InstAlias<"bdztarl+", (gBCTARL 27, CR0LT, 0)>;
+def : InstAlias<"bdztarl-", (gBCTARL 26, CR0LT, 0)>;
+}
+
multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
def : InstAlias<"b"#name#pm#" $cc, $dst",
(BCC (pred bibo, crrc:$cc), condbrtarget:$dst)>;
@@ -5307,6 +5364,18 @@ multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
(BCCCTRL (pred bibo, crrc:$cc))>;
def : InstAlias<"b"#name#"ctrl"#pm,
(BCCCTRL (pred bibo, CR0))>;
+
+ let Predicates = [IsISA2_07] in {
+ def : InstAlias<"b"#name#"tar"#pm#" $cc",
+ (BCCTAR (pred bibo, crrc:$cc))>;
+ def : InstAlias<"b"#name#"tar"#pm,
+ (BCCTAR (pred bibo, CR0))>;
+
+ def : InstAlias<"b"#name#"tarl"#pm#" $cc",
+ (BCCTARL (pred bibo, crrc:$cc))>;
+ def : InstAlias<"b"#name#"tarl"#pm,
+ (BCCTARL (pred bibo, CR0))>;
+ }
}
multiclass BranchExtendedMnemonic<string name, int bibo> {
defm : BranchExtendedMnemonicPM<name, "", bibo>;
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-bctar.s b/llvm/test/MC/PowerPC/ppc64-encoding-bctar.s
new file mode 100644
index 0000000000000..02cf81866a967
--- /dev/null
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-bctar.s
@@ -0,0 +1,111 @@
+# RUN: llvm-mc -triple powerpc64-unknown-linux-gnu -mcpu=pwr8 -show-encoding %s | \
+# RUN: FileCheck -check-prefix=CHECK-BE %s
+# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -show-encoding %s | \
+# RUN: FileCheck -check-prefix=CHECK-LE %s
+
+# ISA 2.07 (POWER8) Branch Conditional to Target Address Register
+
+# bctar (generic form, 3-operand)
+# CHECK-BE: bctar 4, 10, 3 # encoding: [0x4c,0x8a,0x1c,0x60]
+# CHECK-LE: bctar 4, 10, 3 # encoding: [0x60,0x1c,0x8a,0x4c]
+ bctar 4, 10, 3
+# CHECK-BE: bctar 4, 10 # encoding: [0x4c,0x8a,0x04,0x60]
+# CHECK-LE: bctar 4, 10 # encoding: [0x60,0x04,0x8a,0x4c]
+ bctar 4, 10
+# CHECK-BE: bctarl 4, 10, 3 # encoding: [0x4c,0x8a,0x1c,0x61]
+# CHECK-LE: bctarl 4, 10, 3 # encoding: [0x61,0x1c,0x8a,0x4c]
+ bctarl 4, 10, 3
+# CHECK-BE: bctarl 4, 10 # encoding: [0x4c,0x8a,0x04,0x61]
+# CHECK-LE: bctarl 4, 10 # encoding: [0x61,0x04,0x8a,0x4c]
+ bctarl 4, 10
+
+# bttar/bftar (simple mnemonics print as generic bctar)
+# CHECK-BE: bctar 12, 2 # encoding: [0x4d,0x82,0x04,0x60]
+# CHECK-LE: bctar 12, 2 # encoding: [0x60,0x04,0x82,0x4d]
+ bttar 2
+# CHECK-BE: bctar 4, 2 # encoding: [0x4c,0x82,0x04,0x60]
+# CHECK-LE: bctar 4, 2 # encoding: [0x60,0x04,0x82,0x4c]
+ bftar 2
+# CHECK-BE: bctarl 12, 2 # encoding: [0x4d,0x82,0x04,0x61]
+# CHECK-LE: bctarl 12, 2 # encoding: [0x61,0x04,0x82,0x4d]
+ bttarl 2
+# CHECK-BE: bctarl 4, 2 # encoding: [0x4c,0x82,0x04,0x61]
+# CHECK-LE: bctarl 4, 2 # encoding: [0x61,0x04,0x82,0x4c]
+ bftarl 2
+
+# bttar/bftar with prediction hints
+# CHECK-BE: bctar 15, 2 # encoding: [0x4d,0xe2,0x04,0x60]
+# CHECK-LE: bctar 15, 2 # encoding: [0x60,0x04,0xe2,0x4d]
+ bttar+ 2
+# CHECK-BE: bctar 14, 2 # encoding: [0x4d,0xc2,0x04,0x60]
+# CHECK-LE: bctar 14, 2 # encoding: [0x60,0x04,0xc2,0x4d]
+ bttar- 2
+# CHECK-BE: bctar 7, 2 # encoding: [0x4c,0xe2,0x04,0x60]
+# CHECK-LE: bctar 7, 2 # encoding: [0x60,0x04,0xe2,0x4c]
+ bftar+ 2
+# CHECK-BE: bctar 6, 2 # encoding: [0x4c,0xc2,0x04,0x60]
+# CHECK-LE: bctar 6, 2 # encoding: [0x60,0x04,0xc2,0x4c]
+ bftar- 2
+
+# Extended mnemonics (blttar, bgttar, etc.)
+# CHECK-BE: blttar 0 # encoding: [0x4d,0x80,0x04,0x60]
+# CHECK-LE: blttar 0 # encoding: [0x60,0x04,0x80,0x4d]
+ blttar
+# CHECK-BE: blttar 2 # encoding: [0x4d,0x88,0x04,0x60]
+# CHECK-LE: blttar 2 # encoding: [0x60,0x04,0x88,0x4d]
+ blttar 2
+# CHECK-BE: blttarl 0 # encoding: [0x4d,0x80,0x04,0x61]
+# CHECK-LE: blttarl 0 # encoding: [0x61,0x04,0x80,0x4d]
+ blttarl
+# CHECK-BE: blttarl 2 # encoding: [0x4d,0x88,0x04,0x61]
+# CHECK-LE: blttarl 2 # encoding: [0x61,0x04,0x88,0x4d]
+ blttarl 2
+
+# CHECK-BE: bgttar 2 # encoding: [0x4d,0x89,0x04,0x60]
+# CHECK-LE: bgttar 2 # encoding: [0x60,0x04,0x89,0x4d]
+ bgttar 2
+# CHECK-BE: beqtar 2 # encoding: [0x4d,0x8a,0x04,0x60]
+# CHECK-LE: beqtar 2 # encoding: [0x60,0x04,0x8a,0x4d]
+ beqtar 2
+
+# Extended mnemonics with prediction hints
+# CHECK-BE: blttar+ 0 # encoding: [0x4d,0xe0,0x04,0x60]
+# CHECK-LE: blttar+ 0 # encoding: [0x60,0x04,0xe0,0x4d]
+ blttar+
+# CHECK-BE: blttar- 0 # encoding: [0x4d,0xc0,0x04,0x60]
+# CHECK-LE: blttar- 0 # encoding: [0x60,0x04,0xc0,0x4d]
+ blttar-
+# CHECK-BE: blttarl+ 0 # encoding: [0x4d,0xe0,0x04,0x61]
+# CHECK-LE: blttarl+ 0 # encoding: [0x61,0x04,0xe0,0x4d]
+ blttarl+
+# CHECK-BE: blttarl- 0 # encoding: [0x4d,0xc0,0x04,0x61]
+# CHECK-LE: blttarl- 0 # encoding: [0x61,0x04,0xc0,0x4d]
+ blttarl-
+
+# bdnztar/bdztar
+# CHECK-BE: bctar 16, 0, 0 # encoding: [0x4e,0x00,0x04,0x60]
+# CHECK-LE: bctar 16, 0, 0 # encoding: [0x60,0x04,0x00,0x4e]
+ bdnztar
+# CHECK-BE: bctar 18, 0, 0 # encoding: [0x4e,0x40,0x04,0x60]
+# CHECK-LE: bctar 18, 0, 0 # encoding: [0x60,0x04,0x40,0x4e]
+ bdztar
+# CHECK-BE: bctarl 16, 0, 0 # encoding: [0x4e,0x00,0x04,0x61]
+# CHECK-LE: bctarl 16, 0, 0 # encoding: [0x61,0x04,0x00,0x4e]
+ bdnztarl
+# CHECK-BE: bctarl 18, 0, 0 # encoding: [0x4e,0x40,0x04,0x61]
+# CHECK-LE: bctarl 18, 0, 0 # encoding: [0x61,0x04,0x40,0x4e]
+ bdztarl
+
+# bdnztar/bdztar with prediction hints
+# CHECK-BE: bctar 25, 0, 0 # encoding: [0x4f,0x20,0x04,0x60]
+# CHECK-LE: bctar 25, 0, 0 # encoding: [0x60,0x04,0x20,0x4f]
+ bdnztar+
+# CHECK-BE: bctar 24, 0, 0 # encoding: [0x4f,0x00,0x04,0x60]
+# CHECK-LE: bctar 24, 0, 0 # encoding: [0x60,0x04,0x00,0x4f]
+ bdnztar-
+# CHECK-BE: bctar 27, 0, 0 # encoding: [0x4f,0x60,0x04,0x60]
+# CHECK-LE: bctar 27, 0, 0 # encoding: [0x60,0x04,0x60,0x4f]
+ bdztar+
+# CHECK-BE: bctar 26, 0, 0 # encoding: [0x4f,0x40,0x04,0x60]
+# CHECK-LE: bctar 26, 0, 0 # encoding: [0x60,0x04,0x40,0x4f]
+ bdztar-
|
|
Friendly ping — this PR has been approved since 2026-03-20 and has no unresolved feedback. Could you land it when convenient, @nemanjai? Happy to rebase if main has drifted. Thanks for the review. |
lei137
requested changes
Apr 16, 2026
Contributor
There was a problem hiding this comment.
Can you please add some disassembly tests in llvm/test/MC/Disassembler/PowerPC?
I'm wondering if this is missing 64bit support since I see let Defs = [LR] which is the representation for 32bit link register vs the 64bit representation LR8.
See def of BLR vs BLR8
| defm : BranchSimpleMnemonic2<"f", "-", 6>; | ||
| defm : BranchSimpleMnemonic2<"t", "+", 15>; | ||
| defm : BranchSimpleMnemonic2<"f", "+", 7>; | ||
| multiclass BranchSimpleMnemonic3<string name, string pm, int bo> |
Contributor
There was a problem hiding this comment.
Do we really need this new multiclass? Seems this makes BranchSimpleMnemonic2 obsolete so maybe just add the def directly into BranchSimpleMnemonic2?
Scottcjn
added a commit
to Scottcjn/llvm-project
that referenced
this pull request
Apr 17, 2026
…eview) Mirrors the BCCTR/BCCTR8 and BCCTRL/BCCCTRL8 split: 64-bit code paths need variants that Def LR8 rather than LR, matching BLR/BLR8. - BCCTAR8 (non-linking, IsPPC64) in isTerminator/isBarrier scope - BCCTARL8 (linking, IsPPC64) in Defs=[LR8] scope with Uses=[RM] Addresses @lei137 review on llvm#187322.
Scottcjn
added a commit
to Scottcjn/llvm-project
that referenced
this pull request
Apr 17, 2026
New ppc64-encoding-bctar.txt exercises the MC disassembler on both BE and LE powerpc64 for generic bctar/bctarl, simple mnemonics (bttar/bftar), prediction hints, extended mnemonics (blttar/bgttar/beqtar), and the bdnztar/bdztar forms that decode as generic bctar with BO values. Addresses @lei137 review on llvm#187322.
Author
|
Thanks for the review @lei137 — pushed both fixes so both 32-bit and 64-bit are properly covered now: Coverage after these commits:
Both coexist, mirroring the existing 1. 64-bit variants (BCCTAR8 / BCCTARL8) — 3dd27bd Two new blocks in
The existing 32-bit 2. Disassembly tests — 157ed0d New
All bytes match the BE encodings already verified in the paired Caveat: these commits were prepared without a local LLVM rebuild (derived from comparing against Let me know if you want me to also add a 32-bit disassembly test file, or restructure the 64-bit blocks differently. |
Author
|
Thanks for the review @lei137. Addressed all three points: 1. Disassembly testsAdded in
2. 64-bit support (
|
🪟 Windows x64 Test ResultsThe build failed before running any tests. Click on a failure below to see the details. [code=1] lib/Target/PowerPC/PPCGenSubtargetInfo.inc C:/_work/llvm-project/llvm-project/build/lib/Target/PowerPC/PPCGenSubtargetInfo.inc[code=1] lib/Target/PowerPC/PPCGenInstrInfo.inc C:/_work/llvm-project/llvm-project/build/lib/Target/PowerPC/PPCGenInstrInfo.incIf these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the |
🐧 Linux x64 Test ResultsThe build failed before running any tests. Click on a failure below to see the details. lib/Target/PowerPC/PPCGenSubtargetInfo.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/PowerPC/PPCGenSubtargetInfo.inclib/Target/PowerPC/PPCGenInstrInfo.inc /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lib/Target/PowerPC/PPCGenInstrInfo.incIf these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the |
lei137
reviewed
Apr 28, 2026
lei137
left a comment
lei137
left a comment
Contributor
There was a problem hiding this comment.
This patch does not build. Missing scheduling information..
eg. For P10 you need:
diff --git a/llvm/lib/Target/PowerPC/P10InstrResources.td b/llvm/lib/Target/PowerPC/P10InstrResources.td
index 842174239cc4..c5f5d41024e2 100644
--- a/llvm/lib/Target/PowerPC/P10InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P10InstrResources.td
@@ -310,7 +310,7 @@ def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY],
// 2 Cycles Branch operations, 1 input operands
def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read],
(instrs
- B, BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCCLRL, CTRL_DEP, TAILB, TAILB8,
+ B, BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCCLRL, BCCTAR, BCCTAR8, BCCTARL, BCCTARL8, CTRL_DEP, TAILB, TAILB8,
BA, TAILBA, TAILBA8,
BCCTR, BCCTR8, BCCTR8n, BCCTRn, gBCCTR,
BCCTRL, BCCTRL8, BCCTRL8n, BCCTRLn, gBCCTRL,
@@ -1950,6 +1950,8 @@ def : InstRW<[P10W_ST_3C, P10W_DISP_PAIR, P10W_ST_3C, P10ST_Read, P10ST_Read, P1
def : InstRW<[P10W_SX, P10W_DISP_ANY],
(instrs
ATTN,
+ gBCTAR,
+ gBCTARL,
CP_ABORT,
CRNOT,
DCBA,
Similar ones will be needed for the P9, p8, etc..
Is this needed for something specific or just ISA completeness? From what I can see we don't have the TAR register defined in the ppc backend so that would be a prerequisite for these instructions. I don't have the 2.07 ISA handy, but looking at the instruction defInition on ISA3.1 I see "The TAR is reserved for system software.". Which indicates compilers should not normally allocate it, depend on it, or generate code using it for ordinary programs.
Author
|
The two items from the last review are done: the P9/P10 scheduling resources were added (the "missing scheduling info / does not build" issue is resolved, build is green now) and the disassembler tests are in. Should be ready for another look. Thanks. |
Add assembly/disassembly support for the bctar (Branch Conditional to Target Address Register) instruction family, introduced in Power ISA 2.07 (POWER8). The TAR register provides an additional branch target alongside LR and CTR. Instruction definitions added: - gBCTAR/gBCTARL: Generic bctar/bctarl with BO, BI, BH operands - BCCTAR/BCCTARL: Predicated forms for extended mnemonics Mnemonics added: - bctar/bctarl: Base conditional branch to TAR (3-operand and 2-operand) - bttar/bftar/bttarl/bftarl: Simple true/false mnemonics with +/- hints - blttar/bgttar/beqtar/...: Extended condition mnemonics with +/- hints and link variants (blttarl, bgttarl+, etc.) - bdnztar/bdztar: Decrement CTR and branch to TAR, with +/- hints and link variants All new definitions are gated on the IsISA2_07 predicate. Encoding: XL-form with opcode=19, XO=560 (cf. bcctr XO=528, bclr XO=16). Fixes llvm#176864 Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
…eview) Mirrors the BCCTR/BCCTR8 and BCCTRL/BCCCTRL8 split: 64-bit code paths need variants that Def LR8 rather than LR, matching BLR/BLR8. - BCCTAR8 (non-linking, IsPPC64) in isTerminator/isBarrier scope - BCCTARL8 (linking, IsPPC64) in Defs=[LR8] scope with Uses=[RM] Addresses @lei137 review on llvm#187322.
New ppc64-encoding-bctar.txt exercises the MC disassembler on both BE and LE powerpc64 for generic bctar/bctarl, simple mnemonics (bttar/bftar), prediction hints, extended mnemonics (blttar/bgttar/beqtar), and the bdnztar/bdztar forms that decode as generic bctar with BO values. Addresses @lei137 review on llvm#187322.
Per @lei137 review: the parallel multiclass was unnecessary. Extend BranchSimpleMnemonic2 with the ISA 2.07-gated bctar/bctarl aliases directly, drop the BranchSimpleMnemonic3 hop, and keep the defm call sites on BranchSimpleMnemonic2. Net: -6 lines, same generated aliases, no behavioral change.
Lei Huang's review noted the patch fails to build because the new bctar instructions (BCCTAR, BCCTAR8, BCCTARL, BCCTARL8, gBCTAR, gBCTARL) have no scheduling information, and P9/P10 set CompleteModel = 1. P10InstrResources.td: add all six forms to the 2-cycle branch (P10W_BR_2C) group, alongside the analogous BCCTR/gBCCTR entries. P9InstrResources.td: add BCCTAR(L)?(8)? and gBCTAR(L)? instregex entries to the 2-cycle branch (P9_BR_2C) group, alongside the existing BCCTR entries. Only P9 and P10 have CompleteModel = 1; P7/P8 and the older itinerary models (CompleteModel = 0) do not require explicit entries.
These tests never ran in CI: the build failed earlier at the PPC scheduling-model CompleteModel check, so the test phase was never reached. With the build fixed, both files fail as written. ppc64-encoding-bctar.s: the bdnztar/bdztar CHECK lines expected a 3-operand 'bctar BO, 0, 0'. When BH == 0 the instruction prints via the 2-operand 'bctar $bo, $bi' InstAlias, exactly as bcctr does -- so the assembler emits 'bctar BO, 0'. Drop the spurious third operand from the 16 affected CHECK-BE/CHECK-LE lines (encodings were already correct). ppc64-encoding-bctar.txt: the second RUN line disassembled the big-endian instruction bytes under a little-endian triple, decoding them as unrelated 'ori' instructions. The CHECK lines also expected extended mnemonics (blttar/bgttar/beqtar) that the disassembler does not reconstruct. Make the test big-endian only and expect the generic 'bctar/bctarl BO, BI[, BH]' forms the disassembler emits. Verified on POWER8 (ppc64le): full PowerPC backend builds and both tests pass.
Author
|
@lei137 rebased onto current main (8225c81) and re-verified the build failure you hit in April is gone. I checked it rather than assuming it. On the commit before the scheduling-resources commit, That was an x86_64 host with a PowerPC-only Release build, no assertions, and no testing on real Power hardware. The commits are also re-authored off the noreply address, so premerge should be able to run this time. Your review is still marked as requesting changes; the disassembly tests, the 64-bit |
Contributor
I think you might of missed my question/comment from above. |
Contributor
I needed it when trying to assemble bctar using llvm: #176831 (comment) |
Author
|
Sorry Lei, I did miss it. It was in a review thread and I lost track of it, that's on me. On whether it's needed: it's not just ISA completeness. It closes #176864, which @programmerjake filed asking for On TAR, you're right and I should have caught it. There's no TAR register in the backend and I didn't add one. And you're right that the compiler has no business generating these. The What the issue actually asked for is assembler and disassembler support, and the assembler already handles plenty of instructions the compiler never emits because people writing system software still need to assemble them. So my proposal is to strip the codegen-only defs and leave MC support only: assembly, disassembly, the simplified mnemonics, and the tests. No TAR register, no patterns, nothing the register allocator can touch. Let me know if that's the shape you want and I'll push it. If you'd rather see TAR properly modeled as a register first, say so and I'll close this and do that as a prerequisite instead. Your older comment about the new multiclass versus folding into |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
7 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Summary
Add assembly/disassembly support for
bctar(Branch Conditional to Target Address Register), introduced in Power ISA 2.07 (POWER8). The TAR provides an additional indirect branch target alongside LR and CTR.gBCTAR/gBCTARL(generic),BCCTAR/BCCTARL(predicated, codegen-only)bcctrXO=528)bttar/bftar,blttar/bgttar/beqtar/etc.,bdnztar/bdztar, all with+/-hints and link variantsIsISA2_07Fixes #176864
Test plan
llvm/test/MC/PowerPC/ppc64-encoding-bctar.s— assembly + encoding tests for generic, simple, extended, and bdnz/bdz forms (BE and LE)