[AMDGPU] Enable shift64 hazard recognition for gfx9 - #183839
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Signed-off-by: John Lu <John.Lu@amd.com>
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@llvm/pr-subscribers-backend-amdgpu Author: None (LU-JOHN) ChangesEnable shift64 hazard recognition for gfx9 cores. Full diff: https://github.com/llvm/llvm-project/pull/183839.diff 2 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 5dac0c5dd9bd7..0d209511fb12c 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -539,7 +539,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
// Shift amount of a 64 bit shift cannot be a highest allocated register
// if also at the end of the allocation block.
bool hasShift64HighRegBug() const {
- return HasGFX90AInsts && !HasGFX940Insts;
+ return HasGFX90AInsts;
}
// Has one cycle hazard on transcendental instruction feeding a
diff --git a/llvm/test/CodeGen/AMDGPU/hazard-shift64.mir b/llvm/test/CodeGen/AMDGPU/hazard-shift64.mir
index 74c641bebb78b..d349a602c49eb 100644
--- a/llvm/test/CodeGen/AMDGPU/hazard-shift64.mir
+++ b/llvm/test/CodeGen/AMDGPU/hazard-shift64.mir
@@ -1,5 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx950 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN %s
---
name: highest_reg_shift_amt_v7
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LU-JOHN
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✅ With the latest revision this PR passed the C/C++ code formatter. |
Signed-off-by: John Lu <John.Lu@amd.com>
rampitec
approved these changes
Feb 27, 2026
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/66/builds/27155 Here is the relevant piece of the build log for the reference |
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Mar 4, 2026
Enable shift64 hazard recognition for gfx9 cores. --------- Signed-off-by: John Lu <John.Lu@amd.com>
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Mar 5, 2026
Enable shift64 hazard recognition for gfx9 cores. --------- Signed-off-by: John Lu <John.Lu@amd.com>
This was referenced Apr 15, 2026
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Enable shift64 hazard recognition for gfx9 cores.