[SLP][NFC] Precommit test for zext reorder with duplicate shifts - #183748
Merged
Merged
Conversation
Member
|
@llvm/pr-subscribers-llvm-transforms Author: Akash Dutta (akadutta) ChangesThis is a pre-commit test for #183627, Full diff: https://github.com/llvm/llvm-project/pull/183748.diff 1 Files Affected:
diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/zext-duplicate-shift.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/zext-duplicate-shift.ll
new file mode 100644
index 0000000000000..abe95d30a528d
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/zext-duplicate-shift.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S -passes=slp-vectorizer -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s
+
+define void @duplicate_shift_i128_store(ptr %base, i32 %spec_select, i32 %spec_select37, i1 %narrow) {
+; CHECK-LABEL: define void @duplicate_shift_i128_store(
+; CHECK-SAME: ptr [[BASE:%.*]], i32 [[SPEC_SELECT:%.*]], i32 [[SPEC_SELECT37:%.*]], i1 [[NARROW:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 1024
+; CHECK-NEXT: [[P_INSERT_11:%.*]] = select i1 [[NARROW]], i128 158456325046975419260797452288, i128 158456325028528675187087900672
+; CHECK-NEXT: [[ZEXT37:%.*]] = zext i32 [[SPEC_SELECT37]] to i128
+; CHECK-NEXT: [[SHL37:%.*]] = shl nuw nsw i128 [[ZEXT37]], 32
+; CHECK-NEXT: [[MASKED37:%.*]] = and i128 [[SHL37]], 18446742974197923840
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[SPEC_SELECT37]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
+; CHECK-NEXT: [[TMP3:%.*]] = and <4 x i32> [[TMP2]], <i32 16711680, i32 65280, i32 255, i32 255>
+; CHECK-NEXT: [[PREFIX_HIGH:%.*]] = and i32 [[SPEC_SELECT]], -16777216
+; CHECK-NEXT: [[ZEXT_HIGH:%.*]] = zext i32 [[PREFIX_HIGH]] to i128
+; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to i128
+; CHECK-NEXT: [[P_MASK_0:%.*]] = or disjoint i128 [[TMP5]], [[ZEXT_HIGH]]
+; CHECK-NEXT: [[ZEXT_255:%.*]] = or disjoint i128 [[MASKED37]], [[P_INSERT_11]]
+; CHECK-NEXT: [[P_INSERT_0:%.*]] = or disjoint i128 [[P_MASK_0]], [[ZEXT_255]]
+; CHECK-NEXT: store i128 [[P_INSERT_0]], ptr [[ARRAYIDX]], align 16
+; CHECK-NEXT: ret void
+;
+entry:
+ %arrayidx = getelementptr inbounds i8, ptr %base, i64 1024
+ %p_insert_11 = select i1 %narrow, i128 158456325046975419260797452288, i128 158456325028528675187087900672
+ %zext37 = zext i32 %spec_select37 to i128
+ %shl37 = shl nuw nsw i128 %zext37, 32
+ %masked37 = and i128 %shl37, 18446742974197923840
+ %and37_255 = and i32 %spec_select37, 255
+ %zext37_255 = zext nneg i32 %and37_255 to i128
+ %shl37_255 = shl nuw nsw i128 %zext37_255, 32
+ %p_mask_7 = or disjoint i128 %p_insert_11, %masked37
+ %p_insert_7 = or disjoint i128 %p_mask_7, %shl37_255
+ %prefix_high = and i32 %spec_select, -16777216
+ %zext_high = zext i32 %prefix_high to i128
+ %p_insert_6 = or disjoint i128 %p_insert_7, %zext_high
+ %and_16711680 = and i32 %spec_select, 16711680
+ %zext_16711680 = zext nneg i32 %and_16711680 to i128
+ %p_mask_4 = or disjoint i128 %p_insert_6, %zext_16711680
+ %and_255 = and i32 %spec_select, 255
+ %zext_255 = zext nneg i32 %and_255 to i128
+ %and_65280 = and i32 %spec_select, 65280
+ %zext_65280 = zext nneg i32 %and_65280 to i128
+ %p_mask_0 = or disjoint i128 %p_mask_4, %zext_65280
+ %p_insert_0 = or disjoint i128 %p_mask_0, %zext_255
+ ; Generic store i128 (triggers SLP).
+ store i128 %p_insert_0, ptr %arrayidx, align 16
+ ret void
+}
|
Member
|
@llvm/pr-subscribers-backend-amdgpu Author: Akash Dutta (akadutta) ChangesThis is a pre-commit test for #183627, Full diff: https://github.com/llvm/llvm-project/pull/183748.diff 1 Files Affected:
diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/zext-duplicate-shift.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/zext-duplicate-shift.ll
new file mode 100644
index 0000000000000..abe95d30a528d
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/zext-duplicate-shift.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S -passes=slp-vectorizer -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s
+
+define void @duplicate_shift_i128_store(ptr %base, i32 %spec_select, i32 %spec_select37, i1 %narrow) {
+; CHECK-LABEL: define void @duplicate_shift_i128_store(
+; CHECK-SAME: ptr [[BASE:%.*]], i32 [[SPEC_SELECT:%.*]], i32 [[SPEC_SELECT37:%.*]], i1 [[NARROW:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 1024
+; CHECK-NEXT: [[P_INSERT_11:%.*]] = select i1 [[NARROW]], i128 158456325046975419260797452288, i128 158456325028528675187087900672
+; CHECK-NEXT: [[ZEXT37:%.*]] = zext i32 [[SPEC_SELECT37]] to i128
+; CHECK-NEXT: [[SHL37:%.*]] = shl nuw nsw i128 [[ZEXT37]], 32
+; CHECK-NEXT: [[MASKED37:%.*]] = and i128 [[SHL37]], 18446742974197923840
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[SPEC_SELECT37]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
+; CHECK-NEXT: [[TMP3:%.*]] = and <4 x i32> [[TMP2]], <i32 16711680, i32 65280, i32 255, i32 255>
+; CHECK-NEXT: [[PREFIX_HIGH:%.*]] = and i32 [[SPEC_SELECT]], -16777216
+; CHECK-NEXT: [[ZEXT_HIGH:%.*]] = zext i32 [[PREFIX_HIGH]] to i128
+; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to i128
+; CHECK-NEXT: [[P_MASK_0:%.*]] = or disjoint i128 [[TMP5]], [[ZEXT_HIGH]]
+; CHECK-NEXT: [[ZEXT_255:%.*]] = or disjoint i128 [[MASKED37]], [[P_INSERT_11]]
+; CHECK-NEXT: [[P_INSERT_0:%.*]] = or disjoint i128 [[P_MASK_0]], [[ZEXT_255]]
+; CHECK-NEXT: store i128 [[P_INSERT_0]], ptr [[ARRAYIDX]], align 16
+; CHECK-NEXT: ret void
+;
+entry:
+ %arrayidx = getelementptr inbounds i8, ptr %base, i64 1024
+ %p_insert_11 = select i1 %narrow, i128 158456325046975419260797452288, i128 158456325028528675187087900672
+ %zext37 = zext i32 %spec_select37 to i128
+ %shl37 = shl nuw nsw i128 %zext37, 32
+ %masked37 = and i128 %shl37, 18446742974197923840
+ %and37_255 = and i32 %spec_select37, 255
+ %zext37_255 = zext nneg i32 %and37_255 to i128
+ %shl37_255 = shl nuw nsw i128 %zext37_255, 32
+ %p_mask_7 = or disjoint i128 %p_insert_11, %masked37
+ %p_insert_7 = or disjoint i128 %p_mask_7, %shl37_255
+ %prefix_high = and i32 %spec_select, -16777216
+ %zext_high = zext i32 %prefix_high to i128
+ %p_insert_6 = or disjoint i128 %p_insert_7, %zext_high
+ %and_16711680 = and i32 %spec_select, 16711680
+ %zext_16711680 = zext nneg i32 %and_16711680 to i128
+ %p_mask_4 = or disjoint i128 %p_insert_6, %zext_16711680
+ %and_255 = and i32 %spec_select, 255
+ %zext_255 = zext nneg i32 %and_255 to i128
+ %and_65280 = and i32 %spec_select, 65280
+ %zext_65280 = zext nneg i32 %and_65280 to i128
+ %p_mask_0 = or disjoint i128 %p_mask_4, %zext_65280
+ %p_insert_0 = or disjoint i128 %p_mask_0, %zext_255
+ ; Generic store i128 (triggers SLP).
+ store i128 %p_insert_0, ptr %arrayidx, align 16
+ ret void
+}
|
alexey-bataev
approved these changes
Feb 27, 2026
sujianIBM
pushed a commit
to sujianIBM/llvm-project
that referenced
this pull request
Mar 5, 2026
…m#183748) This is a pre-commit test for llvm#183627,
This was referenced Apr 15, 2026
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
3 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
This is a pre-commit test for #183627,