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[AMDGPU][Scheduler] Fix compilation fail in EXPENSIVE_CHECKS - #183745

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lucas-rami merged 1 commit into
llvm:mainfrom
lucas-rami:fix-182853
Feb 27, 2026
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lucas-rami merged 1 commit into
llvm:mainfrom
lucas-rami:fix-182853

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@lucas-rami

@lucas-rami lucas-rami commented Feb 27, 2026

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Bug introduced by #182853 (Remat is now a pointer).

@llvmbot

llvmbot commented Feb 27, 2026

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@llvm/pr-subscribers-backend-amdgpu

Author: Lucas Ramirez (lucas-rami)

Changes

Introduced by #182853 (Remat is now a pointer).


Full diff: https://github.com/llvm/llvm-project/pull/183745.diff

1 Files Affected:

  • (modified) llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp (+1-1)
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index f7ce2272d1149..77c322eb3178e 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -3003,7 +3003,7 @@ MachineInstr *PreRARematStage::ScoredRemat::rematerialize(
     if (LI.hasSubRanges() && MO.getSubReg())
       LM = DAG.TRI->getSubRegIndexLaneMask(MO.getSubReg());
 
-    LaneBitmask LiveInMask = DAG.LiveIns[Remat.UseRegion].at(UseReg);
+    LaneBitmask LiveInMask = DAG.LiveIns[Remat->UseRegion].at(UseReg);
     LaneBitmask UncoveredLanes = LM & ~(LiveInMask & LM);
     // If this register has lanes not covered by the LiveIns, be sure they
     // do not map to any subrange. ref:

@lucas-rami
lucas-rami merged commit a8a6613 into llvm:main Feb 27, 2026
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sujianIBM pushed a commit to sujianIBM/llvm-project that referenced this pull request Mar 5, 2026
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2 participants