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4 changes: 1 addition & 3 deletions llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2776,7 +2776,6 @@ SDValue AMDGPUTargetLowering::LowerFLOGCommon(SDValue Op,
const bool IsLog10 = Op.getOpcode() == ISD::FLOG10;
assert(IsLog10 || Op.getOpcode() == ISD::FLOG);

const auto &Options = getTargetMachine().Options;
if (VT == MVT::f16 || Flags.hasApproximateFuncs()) {

if (VT == MVT::f16 && !isTypeLegal(MVT::f16)) {
Expand Down Expand Up @@ -2845,8 +2844,7 @@ SDValue AMDGPUTargetLowering::LowerFLOGCommon(SDValue Op,
R = getMad(DAG, DL, VT, YH, CH, Mad1);
}

const bool IsFiniteOnly =
(Flags.hasNoNaNs() || Options.NoNaNsFPMath) && Flags.hasNoInfs();
const bool IsFiniteOnly = Flags.hasNoNaNs() && Flags.hasNoInfs();

// TODO: Check if known finite from source value.
if (!IsFiniteOnly) {
Expand Down
7 changes: 1 addition & 6 deletions llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3554,14 +3554,10 @@ bool AMDGPULegalizerInfo::legalizeFlogCommon(MachineInstr &MI,
Register X = MI.getOperand(1).getReg();
unsigned Flags = MI.getFlags();
const LLT Ty = MRI.getType(X);
MachineFunction &MF = B.getMF();

const LLT F32 = LLT::scalar(32);
const LLT F16 = LLT::scalar(16);

const AMDGPUTargetMachine &TM =
static_cast<const AMDGPUTargetMachine &>(MF.getTarget());

if (Ty == F16 || MI.getFlag(MachineInstr::FmAfn)) {
if (Ty == F16 && !ST.has16BitInsts()) {
Register LogVal = MRI.createGenericVirtualRegister(F32);
Expand Down Expand Up @@ -3630,8 +3626,7 @@ bool AMDGPULegalizerInfo::legalizeFlogCommon(MachineInstr &MI,
}

const bool IsFiniteOnly =
(MI.getFlag(MachineInstr::FmNoNans) || TM.Options.NoNaNsFPMath) &&
MI.getFlag(MachineInstr::FmNoInfs);
MI.getFlag(MachineInstr::FmNoNans) && MI.getFlag(MachineInstr::FmNoInfs);

if (!IsFiniteOnly) {
// Expand isfinite(x) => fabs(x) < inf
Expand Down