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Merged
arsenm merged 9 commits into from
Feb 9, 2026
Merged

[GISel] computeKnownBits - add CTLS handling #178063

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4e451ed
add ctls handling in gisel
stomfaig Jan 26, 2026
d6372a0
format
stomfaig Jan 26, 2026
ce6ea5b
add tests
stomfaig Jan 26, 2026
4ae324f
more accurate logic
stomfaig Jan 28, 2026
94ab16b
separate out intrinsic tests for cls
stomfaig Jan 28, 2026
8aafe5b
remove unused random imports
stomfaig Jan 28, 2026
6800b31
resolve comments
stomfaig Jan 29, 2026
e9e1d39
remove duplicate tests
stomfaig Jan 29, 2026
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No auto
arsenm Feb 9, 2026
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24 changes: 24 additions & 0 deletions llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,8 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/APSInt.h"
#include "llvm/ADT/FloatingPointMode.h"
#include "llvm/ADT/ScopeExit.h"
#include "llvm/ADT/StringExtras.h"
Expand All @@ -21,6 +23,7 @@
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineFloatingPointPredicateUtils.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/LowLevelTypeUtils.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
Expand Down Expand Up @@ -681,6 +684,27 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
Known.Zero.setBitsFrom(LowBits);
break;
}
case TargetOpcode::G_CTLS: {
KnownBits SrcOpKnown;
auto Reg = MI.getOperand(1).getReg();
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computeKnownBitsImpl(Reg, SrcOpKnown, DemandedElts, Depth + 1);

@topperc topperc Jan 28, 2026

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Why is this more accurate than using computeNumSignBits like you had before? Doesn't computeNumSignBits use computeKnownBits as a fallback?

@stomfaig stomfaig Jan 28, 2026 •
edited
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The main point is that having SrcOpKnown we can decide if the value is constant. Because if it is, then we know it's ctls exactly.

But if I only use computeNumSignBits, then I would have to excavate the constantness information again, so likely would need to have a computeKnownBitsImpl anyway.

@topperc topperc Jan 28, 2026

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If all the input bits are known, then I hope the input would be constant folded elsewhere. If that's the case, then we should be able to add a combine that constant folds ctls without needing computeKnownBits to do it.

Not using computeNumSignBits prevents us from being able to determine sign bits if the input is a G_SEXT or G_SEXT_INREG. In those cases we know the number of sign bits but not the exact value.

@stomfaig stomfaig Jan 28, 2026

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I see. I was wondering why the G_SEXT and G_SEXT_INREG was not working properly. Thanks for pointing this out.

unsigned MinRedundantSignBits = SrcOpKnown.countMinSignBits() - 1;

if (SrcOpKnown.isConstant()) {
Known = KnownBits::makeConstant(APInt(BitWidth, MinRedundantSignBits));
break;
}

unsigned MaxUpperRedundantSignBits =
MRI.getType(Reg).getScalarSizeInBits() - 1;

ConstantRange Range(APInt(BitWidth, MinRedundantSignBits),
APInt(BitWidth, MaxUpperRedundantSignBits));

Known = Range.toKnownBits();
break;
}
case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
GExtractVectorElement &Extract = cast<GExtractVectorElement>(MI);
Register InVec = Extract.getVectorReg();
Expand Down
192 changes: 192 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/knownbits-ctls.mir
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@@ -0,0 +1,192 @@
# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=aarch64 -passes="print<gisel-value-tracking>" -filetype=null %s 2>&1 | FileCheck %s

---
name: CTLSConst8AmbigousMaxSignbitNum
body: |
bb.1:
; NOTE: Currently we do not estimate max sign bits in KnownBits,
; so while we could get more accurate here, this is currently
; not possible.
; CHECK-LABEL: name: @CTLSConst8AmbigousMaxSignbitNum
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:00110000 SignBits:2
; CHECK-NEXT: %2:_ KnownBits:00001000 SignBits:4
; CHECK-NEXT: %3:_ KnownBits:00??0000 SignBits:2
; CHECK-NEXT: %4:_ KnownBits:00??1000 SignBits:2
; CHECK-NEXT: %5:_ KnownBits:00000??? SignBits:5
%0:_(s8) = COPY $b0
%1:_(s8) = G_CONSTANT i8 48
%2:_(s8) = G_CONSTANT i8 8
%3:_(s8) = G_AND %0, %1
%4:_(s8) = G_OR %3, %2
%5:_(s8) = G_CTLS %4
...

---
name: CTLSNoKnown8
body: |
bb.1:
; CHECK-LABEL: name: @CTLSNoKnown8
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:0000000000000??? SignBits:13
%0:_(s8) = COPY $b0
%1:_(s16) = G_CTLS %0
...

---
name: CTLSNoKnown16
body: |
bb.1:
; CHECK-LABEL: name: @CTLSNoKnown16
; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:000000000000???? SignBits:12
%0:_(s16) = COPY $h0
%1:_(s16) = G_CTLS %0
...

---
name: CTLSNoKnown32
body: |
bb.1:
; CHECK-LABEL: name: @CTLSNoKnown32
; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:00000000000????? SignBits:11
%0:_(s32) = COPY $s0
%1:_(s16) = G_CTLS %0
...


---
name: CTLSHalfKnown8
body: |
bb.1:
; CHECK-LABEL: name: @CTLSHalfKnown8
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:00000100 SignBits:5
; CHECK-NEXT: %2:_ KnownBits:00000?00 SignBits:5
; CHECK-NEXT: %3:_ KnownBits:000001?? SignBits:5
%0:_(s8) = COPY $b0
%1:_(s8) = G_CONSTANT i8 4
%2:_(s8) = G_AND %0, %1
%3:_(s8) = G_CTLS %2
...

---
name: CTLSHalfKnown16
body: |
bb.1:
; CHECK-LABEL: name: @CTLSHalfKnown16
; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:0000000001000000 SignBits:9
; CHECK-NEXT: %2:_ KnownBits:000000000?000000 SignBits:9
; CHECK-NEXT: %3:_ KnownBits:0000000000001??? SignBits:12
%0:_(s16) = COPY $h0
%1:_(s16) = G_CONSTANT i16 64
%2:_(s16) = G_AND %0, %1
%3:_(s16) = G_CTLS %2
...

---
name: CTLSHalfConst8Zero
body: |
bb.1:
; CHECK-LABEL: name: @CTLSHalfConst8Zero
; CHECK-NEXT: %0:_ KnownBits:00000000 SignBits:8
; CHECK-NEXT: %1:_ KnownBits:00000111 SignBits:5
%0:_(s8) = G_CONSTANT i8 0
%1:_(s8) = G_CTLS %0
...

---
name: CTLSHalfConst8NonZero
body: |
bb.1:
; CHECK-LABEL: name: @CTLSHalfConst8NonZero
; CHECK-NEXT: %0:_ KnownBits:00111000 SignBits:2
; CHECK-NEXT: %1:_ KnownBits:00000001 SignBits:7
%0:_(s8) = G_CONSTANT i8 312
%1:_(s8) = G_CTLS %0
...


---
name: CTLSHalfConst16Zero
body: |
bb.1:
; CHECK-LABEL: name: @CTLSHalfConst16Zero
; CHECK-NEXT: %0:_ KnownBits:0000000000000000 SignBits:16
; CHECK-NEXT: %1:_ KnownBits:0000000000001111 SignBits:12
%0:_(s16) = G_CONSTANT i16 0
%1:_(s16) = G_CTLS %0
...

---
name: CTLSHalfConst16NonZero
body: |
bb.1:
; CHECK-LABEL: name: @CTLSHalfConst16NonZero
; CHECK-NEXT: %0:_ KnownBits:0101111011111000 SignBits:1
; CHECK-NEXT: %1:_ KnownBits:0000000000000000 SignBits:16
%0:_(s16) = G_CONSTANT i16 24312
%1:_(s16) = G_CTLS %0
...

---
name: VectorCTLSConst16Zero
body: |
bb.1:
; CHECK-LABEL: name: @VectorCTLSConst16Zero
; CHECK-NEXT: %0:_ KnownBits:0000000000000000 SignBits:16
; CHECK-NEXT: %1:_ KnownBits:0000000000000000 SignBits:16
; CHECK-NEXT: %2:_ KnownBits:0000000000001111 SignBits:12
%0:_(s16) = G_CONSTANT i16 0
%1:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0
%3:_(<4 x s16>) = G_CTLS %1
...

---
name: VectorCTLSConst16NonZero
body: |
bb.1:
; CHECK-LABEL: name: @VectorCTLSConst16NonZero
; CHECK-NEXT: %0:_ KnownBits:0000010011011010 SignBits:5
; CHECK-NEXT: %1:_ KnownBits:0000010011011010 SignBits:5
; CHECK-NEXT: %2:_ KnownBits:0000000000000100 SignBits:13
%0:_(s16) = G_CONSTANT i16 1242
%1:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0
%3:_(<4 x s16>) = G_CTLS %1
...

---
name: VectorCTLSConst8NonZero
body: |
bb.1:
; NOTE: Currently we do not estimate max sign bits in KnownBits,
; so while we could get more accurate here, this is currently
; not possible.
; CHECK-LABEL: name: @VectorCTLSConst8NonZero
; CHECK-NEXT: %0:_ KnownBits:00010111 SignBits:3
; CHECK-NEXT: %1:_ KnownBits:00110010 SignBits:2
; CHECK-NEXT: %2:_ KnownBits:00?10?1? SignBits:2
; CHECK-NEXT: %3:_ KnownBits:00000??? SignBits:5
%0:_(s8) = G_CONSTANT i8 23
%1:_(s8) = G_CONSTANT i8 50
%2:_(<4 x s8>) = G_BUILD_VECTOR %0, %1, %0, %1
%3:_(<4 x s8>) = G_CTLS %2
...

---
name: CTLSLargeEnough
body: |
bb.1:
; CHECK-LABEL: name: @CTLSLargeEnough
; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:0000000000011000 SignBits:11
; CHECK-NEXT: %2:_ KnownBits:00000000000????? SignBits:11
; CHECK-NEXT: %3:_ KnownBits:0000000000001??? SignBits:12
%0:_(s16) = COPY $h0
%1:_(s16) = G_CONSTANT i16 24
%2:_(s16) = G_ASHR %1, %0
%3:_(s16) = G_CTLS %2
...
149 changes: 146 additions & 3 deletions llvm/test/CodeGen/AArch64/arm64-clrsb.ll
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Expand Up @@ -91,6 +91,149 @@ entry:
ret i64 %0
}

;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-GI: {{.*}}
; CHECK-SD: {{.*}}
define i8 @cls_i8(i8 %x) {

@topperc topperc Jan 29, 2026 •
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Can we add a gisel RUN line to llvm/test/CodeGen/AArch64/cls.ll instead of copy and pasting the tests here?

@topperc topperc Jan 29, 2026

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Oh. You already did that. So are these tests duplicated?

@stomfaig stomfaig Jan 29, 2026

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Yes, they are duplicates apart from the mtriple. Will remove.

; CHECK-LABEL: cls_i8:
; CHECK: ; %bb.0:
; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: cls w8, w8
; CHECK-NEXT: sub w0, w8, #24
; CHECK-NEXT: ret

%a = ashr i8 %x, 7
%b = xor i8 %x, %a
%c = call i8 @llvm.ctlz.i8(i8 %b, i1 false)
%d = sub i8 %c, 1
ret i8 %d
}

; The result is in the range [1-31], so we don't need an andi after the cls.
define i32 @cls_i32_knownbits(i32 %x) {
; CHECK-LABEL: cls_i32_knownbits:
; CHECK: ; %bb.0:
; CHECK-NEXT: cls w0, w0
; CHECK-NEXT: ret
%a = ashr i32 %x, 31
%b = xor i32 %x, %a
%c = call i32 @llvm.ctlz.i32(i32 %b, i1 false)
%d = sub i32 %c, 1
%e = and i32 %d, 31
ret i32 %e
}

; There are at least 16 redundant sign bits so we don't need an ori after the cls.
define i32 @cls_i32_knownbits_2(i16 signext %x) {
; CHECK-SD-LABEL: cls_i32_knownbits_2:
; CHECK-SD: ; %bb.0:
; CHECK-SD-NEXT: cls w0, w0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: cls_i32_knownbits_2:
; CHECK-GI: ; %bb.0:
; CHECK-GI-NEXT: cls w8, w0
; CHECK-GI-NEXT: orr w0, w8, #0x10
; CHECK-GI-NEXT: ret
%sext = sext i16 %x to i32
%a = ashr i32 %sext, 31
%b = xor i32 %sext, %a
%c = call i32 @llvm.ctlz.i32(i32 %b, i1 false)
%d = sub i32 %c, 1
%e = or i32 %d, 16
ret i32 %e
}

; Check that the range max in ctls cls knownbits
; is not set to 32
define i64 @cls_i64_not_32(i64 %x) {
; CHECK-SD-LABEL: cls_i64_not_32:
; CHECK-SD: ; %bb.0:
; CHECK-SD-NEXT: asr x8, x0, #16
; CHECK-SD-NEXT: cls x8, x8
; CHECK-SD-NEXT: orr x0, x8, #0x10
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: cls_i64_not_32:
; CHECK-GI: ; %bb.0:
; CHECK-GI-NEXT: asr x8, x0, #63
; CHECK-GI-NEXT: eor x8, x8, x0, asr #16
; CHECK-GI-NEXT: lsl x8, x8, #1
; CHECK-GI-NEXT: orr x8, x8, #0x1
; CHECK-GI-NEXT: clz x8, x8
; CHECK-GI-NEXT: orr x0, x8, #0x10
; CHECK-GI-NEXT: ret
%val = ashr i64 %x, 16
%a = ashr i64 %val, 63
%b = xor i64 %val, %a
%c = shl i64 %b, 1
%d = or i64 %c, 1
%e = call i64 @llvm.ctlz.i64(i64 %d, i1 true)
%f = or i64 %e, 16
ret i64 %f
}

; There are at least 24 redundant sign bits so we don't need an ori after the clsw.
define i32 @cls_i32_knownbits_3(i8 signext %x) {
; CHECK-SD-LABEL: cls_i32_knownbits_3:
; CHECK-SD: ; %bb.0:
; CHECK-SD-NEXT: cls w0, w0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: cls_i32_knownbits_3:
; CHECK-GI: ; %bb.0:
; CHECK-GI-NEXT: cls w8, w0
; CHECK-GI-NEXT: orr w0, w8, #0x18
; CHECK-GI-NEXT: ret
%sext = sext i8 %x to i32
%a = ashr i32 %sext, 31
%b = xor i32 %sext, %a
%c = call i32 @llvm.ctlz.i32(i32 %b, i1 false)
%d = sub i32 %c, 1
%e = or i32 %d, 24
ret i32 %e
}

; Negative test. We only know there is at least 1 redundant sign bit. We can't
; remove the ori.
define i32 @cls_i32_knownbits_4(i32 signext %x) {
; CHECK-LABEL: cls_i32_knownbits_4:
; CHECK: ; %bb.0:
; CHECK-NEXT: sbfx w8, w0, #0, #31
; CHECK-NEXT: cls w8, w8
; CHECK-NEXT: orr w0, w8, #0x1
; CHECK-NEXT: ret
%shl = shl i32 %x, 1
%ashr = ashr i32 %shl, 1
%a = ashr i32 %ashr, 31
%b = xor i32 %ashr, %a
%c = call i32 @llvm.ctlz.i32(i32 %b, i1 false)
%d = sub i32 %c, 1
%e = or i32 %d, 1
ret i32 %e
}

; Negative test. Check that the number of sign bits is not
; overestimated. If it is, the orr disappears.
define i32 @cls_i32_knownbits_no_overestimate(i32 signext %x) {
; CHECK-SD-LABEL: cls_i32_knownbits_no_overestimate:
; CHECK-SD: ; %bb.0:
; CHECK-SD-NEXT: asr w8, w0, #15
; CHECK-SD-NEXT: cls w8, w8
; CHECK-SD-NEXT: orr w0, w8, #0x10
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: cls_i32_knownbits_no_overestimate:
; CHECK-GI: ; %bb.0:
; CHECK-GI-NEXT: asr w8, w0, #31
; CHECK-GI-NEXT: eor w8, w8, w0, asr #15
; CHECK-GI-NEXT: clz w8, w8
; CHECK-GI-NEXT: sub w8, w8, #1
; CHECK-GI-NEXT: orr w0, w8, #0x10
; CHECK-GI-NEXT: ret
%ashr = ashr i32 %x, 15
%a = ashr i32 %ashr, 31
%b = xor i32 %ashr, %a
%c = call i32 @llvm.ctlz.i32(i32 %b, i1 false)
%d = sub i32 %c, 1
%e = or i32 %d, 16
ret i32 %e
}

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