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x86: implement preservenone_cc for 32 bit x86 #177714

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x86: implement preservenone_cc for 32 bit x86 #177714

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76ebf1a
x86: implement preservenone_cc for 32 bit x86
nagisa Jan 24, 2026
f99154d
update calling convention
nagisa Jan 24, 2026
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9 changes: 9 additions & 0 deletions llvm/lib/Target/X86/X86CallingConv.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1032,6 +1032,13 @@ def CC_Intel_OCL_BI : CallingConv<[
CCDelegateTo<CC_X86_32_C>
]>;

// See CC_X86_64_Preserve_None.
def CC_X86_32_Preserve_None : CallingConv<[
CCIfType<[i8, i16], CCPromoteToType<i32>>,
CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX, EDI, ESI]>>,
CCDelegateTo<CC_X86_32_C>
]>;

def CC_X86_64_Preserve_None : CallingConv<[
// We don't preserve general registers, so all of them can be used to pass
// arguments except
Expand Down Expand Up @@ -1072,6 +1079,7 @@ def CC_X86_32 : CallingConv<[
CCIfCC<"CallingConv::X86_RegCall",
CCIfSubtarget<"isTargetWin32()", CCIfRegCallv4<CCDelegateTo<CC_X86_32_RegCallv4_Win>>>>,
CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_32_RegCall>>,
CCIfCC<"CallingConv::PreserveNone", CCDelegateTo<CC_X86_32_Preserve_None>>,

// Otherwise, drop to normal X86-32 CC
CCDelegateTo<CC_X86_32_C>
Expand Down Expand Up @@ -1187,6 +1195,7 @@ def CSR_64_AllRegs_AVX512 : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX,
(sequence "K%u", 0, 7)),
(sequence "XMM%u", 0, 15))>;
def CSR_64_NoneRegs : CalleeSavedRegs<(add RBP)>;
def CSR_32_NoneRegs : CalleeSavedRegs<(add EBP)>;

// Standard C + YMM6-15
def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
Expand Down
6 changes: 4 additions & 2 deletions llvm/lib/Target/X86/X86RegisterInfo.cpp
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Expand Up @@ -244,6 +244,7 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
bool HasSSE = Subtarget.hasSSE1();
bool HasAVX = Subtarget.hasAVX();
bool HasAVX512 = Subtarget.hasAVX512();
bool Is32Bit = Subtarget.is32Bit();
bool CallsEHReturn = MF->callsEHReturn();

CallingConv::ID CC = F.getCallingConv();
Expand Down Expand Up @@ -274,7 +275,7 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
return CSR_64_RT_AllRegs_AVX_SaveList;
return CSR_64_RT_AllRegs_SaveList;
case CallingConv::PreserveNone:
return CSR_64_NoneRegs_SaveList;
return Is32Bit ? CSR_32_NoneRegs_SaveList : CSR_64_NoneRegs_SaveList;
case CallingConv::CXX_FAST_TLS:
if (Is64Bit)
return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ?
Expand Down Expand Up @@ -386,6 +387,7 @@ X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
bool HasSSE = Subtarget.hasSSE1();
bool HasAVX = Subtarget.hasAVX();
bool HasAVX512 = Subtarget.hasAVX512();
bool Is32Bit = Subtarget.is32Bit();

switch (CC) {
case CallingConv::GHC:
Expand All @@ -402,7 +404,7 @@ X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
return CSR_64_RT_AllRegs_AVX_RegMask;
return CSR_64_RT_AllRegs_RegMask;
case CallingConv::PreserveNone:
return CSR_64_NoneRegs_RegMask;
return Is32Bit ? CSR_32_NoneRegs_RegMask : CSR_64_NoneRegs_RegMask;
case CallingConv::CXX_FAST_TLS:
if (Is64Bit)
return CSR_64_TLS_Darwin_RegMask;
Expand Down
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