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AMDGPU: Directly use v2bf16 as register type for bf16 vectors. #175761

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Merged
arsenm merged 1 commit into from
Jan 13, 2026
Merged

AMDGPU: Directly use v2bf16 as register type for bf16 vectors. #175761

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16 changes: 4 additions & 12 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1111,11 +1111,8 @@ MVT SITargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
EVT ScalarVT = VT.getScalarType();
unsigned Size = ScalarVT.getSizeInBits();
if (Size == 16) {
if (Subtarget->has16BitInsts()) {
if (VT.isInteger())
return MVT::v2i16;
return (ScalarVT == MVT::bf16 ? MVT::i32 : MVT::v2f16);
}
if (Subtarget->has16BitInsts())
return MVT::getVectorVT(ScalarVT.getSimpleVT(), 2);
return VT.isInteger() ? MVT::i32 : MVT::f32;
}

Expand Down Expand Up @@ -1167,13 +1164,8 @@ unsigned SITargetLowering::getVectorTypeBreakdownForCallingConv(
// support, but unless we can properly handle 3-vectors, it will be still be
// inconsistent.
if (Size == 16 && Subtarget->has16BitInsts()) {
if (ScalarVT == MVT::bf16) {
RegisterVT = MVT::i32;
IntermediateVT = MVT::v2bf16;
} else {
RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16;
IntermediateVT = RegisterVT;
}
RegisterVT = MVT::getVectorVT(ScalarVT.getSimpleVT(), 2);
IntermediateVT = RegisterVT;
NumIntermediates = (NumElts + 1) / 2;
return NumIntermediates;
}
Expand Down
403 changes: 121 additions & 282 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll
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5 changes: 2 additions & 3 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
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Expand Up @@ -3021,10 +3021,9 @@ define void @void_func_v2bf16_inreg(<2 x bfloat> inreg %arg0) #0 {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr16
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr16
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY]](s32)
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $sgpr16
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK-NEXT: G_STORE [[BITCAST]](<2 x s16>), [[DEF]](p1) :: (store (<2 x s16>) into `ptr addrspace(1) poison`, addrspace 1)
; CHECK-NEXT: G_STORE [[COPY]](<2 x s16>), [[DEF]](p1) :: (store (<2 x s16>) into `ptr addrspace(1) poison`, addrspace 1)
; CHECK-NEXT: SI_RETURN
store <2 x bfloat> %arg0, ptr addrspace(1) poison
ret void
Expand Down
919 changes: 461 additions & 458 deletions llvm/test/CodeGen/AMDGPU/bf16.ll
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2 changes: 0 additions & 2 deletions llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
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Expand Up @@ -2403,7 +2403,6 @@ define amdgpu_vs <2 x bfloat> @load_v2bf16(ptr addrspace(6) inreg %p0, ptr addrs
; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX8-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: load_v2bf16:
Expand Down Expand Up @@ -2438,7 +2437,6 @@ define amdgpu_vs <2 x bfloat> @load_v2bf16(ptr addrspace(6) inreg %p0, ptr addrs
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_and_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
%gep1 = getelementptr inbounds <2 x bfloat>, ptr addrspace(6) %p1, i32 2
%r0 = load <2 x bfloat>, ptr addrspace(6) %p0
Expand Down
255 changes: 122 additions & 133 deletions llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
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38 changes: 14 additions & 24 deletions llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
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Expand Up @@ -127,25 +127,20 @@ define <2 x bfloat> @v_log2_fabs_v2bf16(<2 x bfloat> %in) {
; GFX-SDAG-TRUE16: ; %bb.0:
; GFX-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX-SDAG-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0
; GFX-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 15
; GFX-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e32 v0.l, v1.l
; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e32 v0.h, v2.l
; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e64 v0.h, |v0.h|
; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e64 v0.l, |v0.l|
; GFX-SDAG-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX-SDAG-FAKE16-LABEL: v_log2_fabs_v2bf16:
; GFX-SDAG-FAKE16: ; %bb.0:
; GFX-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX-SDAG-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0
; GFX-SDAG-FAKE16-NEXT: v_bfe_u32 v0, v0, 16, 15
; GFX-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX-SDAG-FAKE16-NEXT: v_log_bf16_e32 v1, v1
; GFX-SDAG-FAKE16-NEXT: v_log_bf16_e32 v0, v0
; GFX-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX-SDAG-FAKE16-NEXT: v_log_bf16_e64 v0, |v0|
; GFX-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX-SDAG-FAKE16-NEXT: v_log_bf16_e64 v1, |v1|
; GFX-SDAG-FAKE16-NEXT: v_nop
; GFX-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX-SDAG-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x5040100
; GFX-SDAG-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX-SDAG-FAKE16-NEXT: s_set_pc_i64 s[30:31]
%fabs = call <2 x bfloat> @llvm.fabs.v2bf16(<2 x bfloat> %in)
%result = call <2 x bfloat> @llvm.log2.v2bf16(<2 x bfloat> %fabs)
Expand All @@ -157,25 +152,20 @@ define <2 x bfloat> @v_log2_fneg_fabs_v2bf16(<2 x bfloat> %in) {
; GFX-SDAG-TRUE16: ; %bb.0:
; GFX-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX-SDAG-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0
; GFX-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 15
; GFX-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e64 v0.l, -v1.l
; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e64 v0.h, -v2.l
; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e64 v0.h, -|v0.h|
; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e64 v0.l, -|v0.l|
; GFX-SDAG-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX-SDAG-FAKE16-LABEL: v_log2_fneg_fabs_v2bf16:
; GFX-SDAG-FAKE16: ; %bb.0:
; GFX-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX-SDAG-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0
; GFX-SDAG-FAKE16-NEXT: v_bfe_u32 v0, v0, 16, 15
; GFX-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX-SDAG-FAKE16-NEXT: v_log_bf16_e64 v1, -v1
; GFX-SDAG-FAKE16-NEXT: v_log_bf16_e64 v0, -v0
; GFX-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX-SDAG-FAKE16-NEXT: v_log_bf16_e64 v0, -|v0|
; GFX-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX-SDAG-FAKE16-NEXT: v_log_bf16_e64 v1, -|v1|
; GFX-SDAG-FAKE16-NEXT: v_nop
; GFX-SDAG-FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
; GFX-SDAG-FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x5040100
; GFX-SDAG-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX-SDAG-FAKE16-NEXT: s_set_pc_i64 s[30:31]
%fabs = call <2 x bfloat> @llvm.fabs.v2bf16(<2 x bfloat> %in)
%fneg.fabs = fneg <2 x bfloat> %fabs
Expand Down
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