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[RISCV] Improve load/store pairing for Xqcilsm instructions in RISCVLoadStoreOptimizer #174612

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Merged
svs-quic merged 3 commits into from
Jan 7, 2026
Merged

[RISCV] Improve load/store pairing for Xqcilsm instructions in RISCVLoadStoreOptimizer #174612

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c397331
Pre-commit tests
svs-quic Jan 6, 2026
83ccdae
Dont iterate over the second instruction when we dont merge
svs-quic Jan 6, 2026
7816c4d
Merge branch 'main' into lstm
svs-quic Jan 7, 2026
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18 changes: 14 additions & 4 deletions llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -482,10 +482,13 @@ RISCVLoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
bool MergeForward) {
MachineBasicBlock::iterator E = I->getParent()->end();
MachineBasicBlock::iterator NextI = next_nodbg(I, E);
// If NextI is the second of the two instructions to be merged, we need
// to skip one further. Either way we merge will invalidate the iterator,
// and we don't need to scan the new instruction, as it's a pairwise
// instruction, which we're not considering for further action anyway.
// If NextI is the second of the two instructions to be merged, skip one
// further for now. For the MIPS load/store, the merge will invalidate the
// iterator, and we don't need to scan the new instruction, as it's a pairwise
// instruction, which we're not considering for further action anyway. For the
// Xqcilsm load/store, we may not want to do this as the second instruction
// could possibly be the first in another pair if we do not merge here. This
// is handled is the else block after the call to tryConvertToLdStPair below.
if (NextI == Paired)
NextI = next_nodbg(NextI, E);

Expand Down Expand Up @@ -535,9 +538,16 @@ RISCVLoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
First = InsertionPoint;
}

MachineFunction *MF = I->getMF();
const RISCVSubtarget &STI = MF->getSubtarget<RISCVSubtarget>();

if (tryConvertToLdStPair(First, Second)) {
LLVM_DEBUG(dbgs() << "Pairing load/store:\n ");
LLVM_DEBUG(prev_nodbg(NextI, MBB.begin())->print(dbgs()));
} else if (!STI.is64Bit() && STI.hasVendorXqcilsm()) {
// We were unable to form the pair, so use the next non-debug instruction
// after the first instruction we had wanted to merge.
NextI = next_nodbg(I, E);
}

return NextI;
Expand Down
57 changes: 57 additions & 0 deletions llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi.mir
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Expand Up @@ -19,6 +19,9 @@
define void @no_pair_if_rd_is_x0_swmi() nounwind { ret void }
define void @pair_if_rd_is_x0_setwmi() nounwind { ret void }
define void @no_pair_if_lw_rd_equals_base() nounwind { ret void }
define void @second_pair_if_no_first_pair_lwmi() nounwind { ret void }
define void @second_pair_if_no_first_pair_swmi() nounwind { ret void }
define void @second_pair_if_no_first_pair_setwmi() nounwind { ret void }
define void @pair_if_not_adjacent() nounwind { ret void }
define void @pair_if_not_adjacent_use() nounwind { ret void }
define void @no_pair_if_not_adjacent_use() nounwind { ret void }
Expand Down Expand Up @@ -292,6 +295,60 @@ body: |
$x11 = LW $x10, 24 :: (load (s32), align 4)
PseudoRET

...
---
name: second_pair_if_no_first_pair_lwmi
tracksRegLiveness: false
body: |
bb.0:
liveins: $x10
; CHECK-LABEL: name: second_pair_if_no_first_pair_lwmi
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x0 = LW $x10, 0 :: (load (s32))
; CHECK-NEXT: $x1 = QC_LWMI $x10, 2, 4, implicit-def $x2 :: (load (s32))
; CHECK-NEXT: PseudoRET
$x0 = LW $x10, 0 :: (load (s32), align 4)
$x1 = LW $x10, 4 :: (load (s32), align 4)
$x2 = LW $x10, 8 :: (load (s32), align 4)
PseudoRET

...
---
name: second_pair_if_no_first_pair_swmi
tracksRegLiveness: false
body: |
bb.0:
liveins: $x10
; CHECK-LABEL: name: second_pair_if_no_first_pair_swmi
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: SW $x0, $x10, 0 :: (store (s32))
; CHECK-NEXT: QC_SWMI $x1, $x10, 2, 4, implicit $x2 :: (store (s32))
; CHECK-NEXT: PseudoRET
SW $x0, $x10, 0 :: (store (s32), align 4)
SW $x1, $x10, 4 :: (store (s32), align 4)
SW $x2, $x10, 8 :: (store (s32), align 4)
PseudoRET

...
---
name: second_pair_if_no_first_pair_setwmi
tracksRegLiveness: false
body: |
bb.0:
liveins: $x10
; CHECK-LABEL: name: second_pair_if_no_first_pair_setwmi
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: SW $x0, $x10, 0 :: (store (s32))
; CHECK-NEXT: QC_SETWMI $x2, $x10, 2, 4 :: (store (s32))
; CHECK-NEXT: PseudoRET
SW $x0, $x10, 0 :: (store (s32), align 4)
SW $x2, $x10, 4 :: (store (s32), align 4)
SW $x2, $x10, 8 :: (store (s32), align 4)
PseudoRET

...
---
# FIXME: Kill flags are not propagated correctly for the base register
Expand Down
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