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Merged
andykaylor merged 20 commits into from
Jan 7, 2026
Merged

[CIR][X86]Implement handling for convert-half builtins #173143

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0dd977d
Implement handling for convert-half builtins
Priyanshu3820 Dec 20, 2025
ed01553
Update CIRGenBuiltinX86.cpp
Priyanshu3820 Dec 20, 2025
50e380f
Update CIRGenBuiltinX86.cpp
Priyanshu3820 Dec 20, 2025
b238c17
Update CIRGenBuiltinsX86.cpp
Priyanshu3820 Dec 20, 2025
9d3a326
add support for maskz builtins
Priyanshu3820 Dec 20, 2025
d2118e6
Update CIRGenBuiltinX86.cpp
Priyanshu3820 Dec 20, 2025
4717d1c
Merge branch 'main' into x86-cvt-half-restart
Priyanshu3820 Dec 20, 2025
72d3ccc
Guard cast to cir::VectorType
Priyanshu3820 Dec 21, 2025
a37cef2
Update CIRGenBuiltinX86.cpp and test
Priyanshu3820 Dec 21, 2025
cf040a0
Update CIRGenBuiltinX86.cpp
Priyanshu3820 Dec 22, 2025
00037b3
Fix formatting
Priyanshu3820 Dec 22, 2025
9e570f3
Fix syntax error
Priyanshu3820 Dec 22, 2025
3292431
Update CIRGenBuiltinX86.cpp
Priyanshu3820 Dec 22, 2025
ac275a9
Update CIRGenBuiltinX86.cpp and test
Priyanshu3820 Dec 22, 2025
2e6c997
Update Test
Priyanshu3820 Dec 22, 2025
b985206
Update CIRGenBuiltinX86.cpp
Priyanshu3820 Dec 22, 2025
a1b47ad
Update CIRGenBuiltinX86.cpp
Priyanshu3820 Dec 22, 2025
591bda3
Update clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
Priyanshu3820 Jan 6, 2026
9e72a9a
Fix formatting and syntax error
Priyanshu3820 Jan 6, 2026
6756bde
Merge branch 'main' into x86-cvt-half-restart
Priyanshu3820 Jan 7, 2026
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35 changes: 33 additions & 2 deletions clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1880,9 +1880,40 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) {
return emitX86CvtF16ToFloatExpr(builder, loc, ops,
convertType(expr->getType()));
}
case X86::BI__builtin_ia32_cvtneps2bf16_128_mask:
case X86::BI__builtin_ia32_cvtneps2bf16_128_mask: {
mlir::Location loc = getLoc(expr->getExprLoc());
cir::VectorType resTy = cast<cir::VectorType>(convertType(expr->getType()));

cir::VectorType inputTy = cast<cir::VectorType>(ops[0].getType());
unsigned numElts = inputTy.getSize();

mlir::Value mask = getMaskVecValue(builder, loc, ops[2], numElts);

SmallVector<mlir::Value, 3> args;
args.push_back(ops[0]);
args.push_back(ops[1]);
args.push_back(mask);

return emitIntrinsicCallOp(
builder, loc, "x86.avx512bf16.mask.cvtneps2bf16.128", resTy, args);
}
case X86::BI__builtin_ia32_cvtneps2bf16_256_mask:
case X86::BI__builtin_ia32_cvtneps2bf16_512_mask:
case X86::BI__builtin_ia32_cvtneps2bf16_512_mask: {
mlir::Location loc = getLoc(expr->getExprLoc());
cir::VectorType resTy = cast<cir::VectorType>(convertType(expr->getType()));
StringRef intrinsicName;
if (builtinID == X86::BI__builtin_ia32_cvtneps2bf16_256_mask) {
intrinsicName = "x86.avx512bf16.cvtneps2bf16.256";
} else {
assert(builtinID == X86::BI__builtin_ia32_cvtneps2bf16_512_mask);
intrinsicName = "x86.avx512bf16.cvtneps2bf16.512";
}

mlir::Value res = emitIntrinsicCallOp(builder, loc, intrinsicName, resTy,
mlir::ValueRange{ops[0]});

return emitX86Select(builder, loc, ops[2], res, ops[1]);
}
case X86::BI__cpuid:
case X86::BI__cpuidex:
case X86::BI__emul:
Expand Down
81 changes: 81 additions & 0 deletions clang/test/CIR/CodeGenBuiltins/X86/avx512vlbf16-builtins.c
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Original file line number Diff line number Diff line change
@@ -0,0 +1,81 @@
// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl -target-feature +avx512bf16 -fclangir -emit-cir -o %t.cir -Wall -Werror -Wsign-conversion
// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl -target-feature +avx512bf16 -fclangir -emit-llvm -o %t.ll -Wall -Werror -Wsign-conversion
// RUN: FileCheck --check-prefixes=LLVM --input-file=%t.ll %s
// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl -target-feature +avx512bf16 -emit-llvm -o %t.ll -Wall -Werror -Wsign-conversion
// RUN: FileCheck --check-prefixes=OGCG --input-file=%t.ll %s

#include <immintrin.h>

__m256bh test_mm512_mask_cvtneps_pbh(__m256bh src, __mmask16 k, __m512 a) {
// CIR-LABEL: test_mm512_mask_cvtneps_pbh
// CIR: cir.call @_mm512_mask_cvtneps_pbh({{.+}}, {{.+}}, {{.+}}) : (!cir.vector<16 x !cir.bf16>, !u16i, !cir.vector<16 x !cir.float>) -> !cir.vector<16 x !cir.bf16>

// LLVM-LABEL: @test_mm512_mask_cvtneps_pbh
// LLVM: call <16 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.512

// OGCG-LABEL: @test_mm512_mask_cvtneps_pbh
// OGCG: call <16 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.512
return _mm512_mask_cvtneps_pbh(src, k, a);
}

__m256bh test_mm512_maskz_cvtneps_pbh(__mmask16 k, __m512 a) {
// CIR-LABEL: test_mm512_maskz_cvtneps_pbh
// CIR: cir.call @_mm512_maskz_cvtneps_pbh({{.+}}, {{.+}}) : (!u16i, !cir.vector<16 x !cir.float>) -> !cir.vector<16 x !cir.bf16>

// LLVM-LABEL: @test_mm512_maskz_cvtneps_pbh
// LLVM: call <16 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.512(<16 x float> {{.+}})

// OGCG-LABEL: @test_mm512_maskz_cvtneps_pbh
// OGCG: call <16 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.512(<16 x float> {{.+}})
return _mm512_maskz_cvtneps_pbh(k, a);
}


__m128bh test_mm256_mask_cvtneps_pbh(__m128bh src, __mmask8 k, __m256 a) {
// CIR-LABEL: test_mm256_mask_cvtneps_pbh
// CIR: cir.call @_mm256_mask_cvtneps_pbh({{.+}}, {{.+}}, {{.+}}) : (!cir.vector<8 x !cir.bf16>, !u8i, !cir.vector<8 x !cir.float>) -> !cir.vector<8 x !cir.bf16>

// LLVM-LABEL: @test_mm256_mask_cvtneps_pbh
// LLVM: call <8 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.256(<8 x float> {{.+}})

// OGCG-LABEL: @test_mm256_mask_cvtneps_pbh
// OGCG: call <8 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.256(<8 x float> {{.+}})
return _mm256_mask_cvtneps_pbh(src, k, a);
}

__m128bh test_mm256_maskz_cvtneps_pbh(__mmask8 k, __m256 a) {
// CIR-LABEL: test_mm256_maskz_cvtneps_pbh
// CIR: cir.call @_mm256_maskz_cvtneps_pbh({{.+}}, {{.+}}) : (!u8i, !cir.vector<8 x !cir.float>) -> !cir.vector<8 x !cir.bf16>

// LLVM-LABEL: @test_mm256_maskz_cvtneps_pbh
// LLVM: call <8 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.256(<8 x float> {{.+}})

// OGCG-LABEL: @test_mm256_maskz_cvtneps_pbh
// OGCG: call <8 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.256(<8 x float> {{.+}})
return _mm256_maskz_cvtneps_pbh(k, a);
}

__m128bh test_mm_mask_cvtneps_pbh(__m128bh src, __mmask8 k, __m128 a) {
// CIR-LABEL: test_mm_mask_cvtneps_pbh
// CIR: cir.call @_mm_mask_cvtneps_pbh({{.+}}, {{.+}}, {{.+}}) : (!cir.vector<8 x !cir.bf16>, !u8i, !cir.vector<4 x !cir.float>) -> !cir.vector<8 x !cir.bf16>{{.+}}

// LLVM-LABEL: @test_mm_mask_cvtneps_pbh
// LLVM: call <8 x bfloat> @llvm.x86.avx512bf16.mask.cvtneps2bf16.128(<4 x float> {{.+}}, <8 x bfloat> {{.+}}, <4 x i1> {{.+}})

// OGCG-LABEL: @test_mm_mask_cvtneps_pbh
// OGCG: call <8 x bfloat> @llvm.x86.avx512bf16.mask.cvtneps2bf16.128(<4 x float> {{.+}}, <8 x bfloat> {{.+}}, <4 x i1> {{.+}})
return _mm_mask_cvtneps_pbh(src, k, a);
}

__m128bh test_mm_maskz_cvtneps_pbh(__mmask8 k, __m128 a) {
// CIR-LABEL: test_mm_maskz_cvtneps_pbh
// CIR: cir.call @_mm_maskz_cvtneps_pbh({{.+}}, {{.+}}) : (!u8i, !cir.vector<4 x !cir.float>) -> !cir.vector<8 x !cir.bf16>

// LLVM-LABEL: @test_mm_maskz_cvtneps_pbh
// LLVM: call <8 x bfloat> @llvm.x86.avx512bf16.mask.cvtneps2bf16.128(<4 x float> {{.+}}, <8 x bfloat> {{.+}}, <4 x i1> {{.+}})

// OGCG-LABEL: @test_mm_maskz_cvtneps_pbh
// OGCG: call <8 x bfloat> @llvm.x86.avx512bf16.mask.cvtneps2bf16.128(<4 x float> {{.+}}, <8 x bfloat> {{.+}}, <4 x i1> {{.+}})
return _mm_maskz_cvtneps_pbh(k, a);
}