[PowerPC] TableGen-erate SDNode descriptions#168108
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s-barannikov merged 4 commits intollvm:mainfrom Nov 17, 2025
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@llvm/pr-subscribers-backend-powerpc Author: Sergei Barannikov (s-barannikov) ChangesThis allows SDNodes to be validated against their expected type profiles and reduces the number of changes required to add a new node. The validation functionality has detected a few issues, see Most of the nodes have a description in Part of #119709. Patch is 70.58 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/168108.diff 10 Files Affected:
diff --git a/llvm/lib/Target/PowerPC/CMakeLists.txt b/llvm/lib/Target/PowerPC/CMakeLists.txt
index 2182039e0eef8..53d565013c4bc 100644
--- a/llvm/lib/Target/PowerPC/CMakeLists.txt
+++ b/llvm/lib/Target/PowerPC/CMakeLists.txt
@@ -11,6 +11,7 @@ tablegen(LLVM PPCGenFastISel.inc -gen-fast-isel)
tablegen(LLVM PPCGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM PPCGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM PPCGenRegisterInfo.inc -gen-register-info)
+tablegen(LLVM PPCGenSDNodeInfo.inc -gen-sd-node-info)
tablegen(LLVM PPCGenSubtargetInfo.inc -gen-subtarget)
tablegen(LLVM PPCGenExegesis.inc -gen-exegesis)
tablegen(LLVM PPCGenRegisterBank.inc -gen-register-bank)
diff --git a/llvm/lib/Target/PowerPC/PPCFastISel.cpp b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
index ea4e597d0fd7d..ca3fe18273ff5 100644
--- a/llvm/lib/Target/PowerPC/PPCFastISel.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
@@ -17,6 +17,7 @@
#include "PPCCallingConv.h"
#include "PPCISelLowering.h"
#include "PPCMachineFunctionInfo.h"
+#include "PPCSelectionDAGInfo.h"
#include "PPCSubtarget.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/FastISel.h"
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 89165fa8f8fdb..dd537c204cec1 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -16,6 +16,7 @@
#include "PPC.h"
#include "PPCISelLowering.h"
#include "PPCMachineFunctionInfo.h"
+#include "PPCSelectionDAGInfo.h"
#include "PPCSubtarget.h"
#include "PPCTargetMachine.h"
#include "llvm/ADT/APInt.h"
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index f55336bafd251..220010c4d3d34 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -20,6 +20,7 @@
#include "PPCMachineFunctionInfo.h"
#include "PPCPerfectShuffle.h"
#include "PPCRegisterInfo.h"
+#include "PPCSelectionDAGInfo.h"
#include "PPCSubtarget.h"
#include "PPCTargetMachine.h"
#include "llvm/ADT/APFloat.h"
@@ -1678,190 +1679,6 @@ bool PPCTargetLowering::shallExtractConstSplatVectorElementToStore(
return false;
}
-const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
- switch ((PPCISD::NodeType)Opcode) {
- case PPCISD::FIRST_NUMBER: break;
- case PPCISD::FSEL: return "PPCISD::FSEL";
- case PPCISD::XSMAXC: return "PPCISD::XSMAXC";
- case PPCISD::XSMINC: return "PPCISD::XSMINC";
- case PPCISD::FCFID: return "PPCISD::FCFID";
- case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
- case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
- case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
- case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
- case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
- case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
- case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
- case PPCISD::FRE: return "PPCISD::FRE";
- case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
- case PPCISD::FTSQRT:
- return "PPCISD::FTSQRT";
- case PPCISD::FSQRT:
- return "PPCISD::FSQRT";
- case PPCISD::STFIWX: return "PPCISD::STFIWX";
- case PPCISD::VPERM: return "PPCISD::VPERM";
- case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
- case PPCISD::XXSPLTI_SP_TO_DP:
- return "PPCISD::XXSPLTI_SP_TO_DP";
- case PPCISD::XXSPLTI32DX:
- return "PPCISD::XXSPLTI32DX";
- case PPCISD::VECINSERT: return "PPCISD::VECINSERT";
- case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI";
- case PPCISD::XXPERM:
- return "PPCISD::XXPERM";
- case PPCISD::VECSHL: return "PPCISD::VECSHL";
- case PPCISD::VSRQ:
- return "PPCISD::VSRQ";
- case PPCISD::CMPB: return "PPCISD::CMPB";
- case PPCISD::Hi: return "PPCISD::Hi";
- case PPCISD::Lo: return "PPCISD::Lo";
- case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
- case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
- case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
- case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
- case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
- case PPCISD::PROBED_ALLOCA: return "PPCISD::PROBED_ALLOCA";
- case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
- case PPCISD::SRL: return "PPCISD::SRL";
- case PPCISD::SRA: return "PPCISD::SRA";
- case PPCISD::SHL: return "PPCISD::SHL";
- case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
- case PPCISD::CALL: return "PPCISD::CALL";
- case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
- case PPCISD::CALL_NOTOC: return "PPCISD::CALL_NOTOC";
- case PPCISD::CALL_RM:
- return "PPCISD::CALL_RM";
- case PPCISD::CALL_NOP_RM:
- return "PPCISD::CALL_NOP_RM";
- case PPCISD::CALL_NOTOC_RM:
- return "PPCISD::CALL_NOTOC_RM";
- case PPCISD::MTCTR: return "PPCISD::MTCTR";
- case PPCISD::BCTRL: return "PPCISD::BCTRL";
- case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
- case PPCISD::BCTRL_RM:
- return "PPCISD::BCTRL_RM";
- case PPCISD::BCTRL_LOAD_TOC_RM:
- return "PPCISD::BCTRL_LOAD_TOC_RM";
- case PPCISD::RET_GLUE: return "PPCISD::RET_GLUE";
- case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
- case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
- case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
- case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
- case PPCISD::MFVSR: return "PPCISD::MFVSR";
- case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
- case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
- case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
- case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
- case PPCISD::SCALAR_TO_VECTOR_PERMUTED:
- return "PPCISD::SCALAR_TO_VECTOR_PERMUTED";
- case PPCISD::ANDI_rec_1_EQ_BIT:
- return "PPCISD::ANDI_rec_1_EQ_BIT";
- case PPCISD::ANDI_rec_1_GT_BIT:
- return "PPCISD::ANDI_rec_1_GT_BIT";
- case PPCISD::VCMP: return "PPCISD::VCMP";
- case PPCISD::VCMP_rec: return "PPCISD::VCMP_rec";
- case PPCISD::LBRX: return "PPCISD::LBRX";
- case PPCISD::STBRX: return "PPCISD::STBRX";
- case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
- case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
- case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
- case PPCISD::STXSIX: return "PPCISD::STXSIX";
- case PPCISD::VEXTS: return "PPCISD::VEXTS";
- case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
- case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
- case PPCISD::LOAD_VEC_BE: return "PPCISD::LOAD_VEC_BE";
- case PPCISD::STORE_VEC_BE: return "PPCISD::STORE_VEC_BE";
- case PPCISD::ST_VSR_SCAL_INT:
- return "PPCISD::ST_VSR_SCAL_INT";
- case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
- case PPCISD::BDNZ: return "PPCISD::BDNZ";
- case PPCISD::BDZ: return "PPCISD::BDZ";
- case PPCISD::MFFS: return "PPCISD::MFFS";
- case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
- case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
- case PPCISD::CR6SET: return "PPCISD::CR6SET";
- case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
- case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
- case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
- case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
- case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
- case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
- case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
- case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
- case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
- case PPCISD::GET_TLS_MOD_AIX: return "PPCISD::GET_TLS_MOD_AIX";
- case PPCISD::GET_TPOINTER: return "PPCISD::GET_TPOINTER";
- case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
- case PPCISD::TLSGD_AIX: return "PPCISD::TLSGD_AIX";
- case PPCISD::TLSLD_AIX: return "PPCISD::TLSLD_AIX";
- case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
- case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
- case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
- case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
- case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
- case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
- case PPCISD::PADDI_DTPREL:
- return "PPCISD::PADDI_DTPREL";
- case PPCISD::VADD_SPLAT:
- return "PPCISD::VADD_SPLAT";
- case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
- case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
- case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
- case PPCISD::BUILD_SPE64: return "PPCISD::BUILD_SPE64";
- case PPCISD::EXTRACT_SPE: return "PPCISD::EXTRACT_SPE";
- case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
- case PPCISD::LD_VSX_LH: return "PPCISD::LD_VSX_LH";
- case PPCISD::FP_EXTEND_HALF: return "PPCISD::FP_EXTEND_HALF";
- case PPCISD::MAT_PCREL_ADDR: return "PPCISD::MAT_PCREL_ADDR";
- case PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR:
- return "PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR";
- case PPCISD::TLS_LOCAL_EXEC_MAT_ADDR:
- return "PPCISD::TLS_LOCAL_EXEC_MAT_ADDR";
- case PPCISD::ACC_BUILD: return "PPCISD::ACC_BUILD";
- case PPCISD::PAIR_BUILD: return "PPCISD::PAIR_BUILD";
- case PPCISD::EXTRACT_VSX_REG: return "PPCISD::EXTRACT_VSX_REG";
- case PPCISD::XXMFACC: return "PPCISD::XXMFACC";
- case PPCISD::LD_SPLAT: return "PPCISD::LD_SPLAT";
- case PPCISD::ZEXT_LD_SPLAT: return "PPCISD::ZEXT_LD_SPLAT";
- case PPCISD::SEXT_LD_SPLAT: return "PPCISD::SEXT_LD_SPLAT";
- case PPCISD::FNMSUB: return "PPCISD::FNMSUB";
- case PPCISD::STRICT_FADDRTZ:
- return "PPCISD::STRICT_FADDRTZ";
- case PPCISD::STRICT_FCTIDZ:
- return "PPCISD::STRICT_FCTIDZ";
- case PPCISD::STRICT_FCTIWZ:
- return "PPCISD::STRICT_FCTIWZ";
- case PPCISD::STRICT_FCTIDUZ:
- return "PPCISD::STRICT_FCTIDUZ";
- case PPCISD::STRICT_FCTIWUZ:
- return "PPCISD::STRICT_FCTIWUZ";
- case PPCISD::STRICT_FCFID:
- return "PPCISD::STRICT_FCFID";
- case PPCISD::STRICT_FCFIDU:
- return "PPCISD::STRICT_FCFIDU";
- case PPCISD::STRICT_FCFIDS:
- return "PPCISD::STRICT_FCFIDS";
- case PPCISD::STRICT_FCFIDUS:
- return "PPCISD::STRICT_FCFIDUS";
- case PPCISD::LXVRZX: return "PPCISD::LXVRZX";
- case PPCISD::STORE_COND:
- return "PPCISD::STORE_COND";
- case PPCISD::SETBC:
- return "PPCISD::SETBC";
- case PPCISD::SETBCR:
- return "PPCISD::SETBCR";
- case PPCISD::ADDC:
- return "PPCISD::ADDC";
- case PPCISD::ADDE:
- return "PPCISD::ADDE";
- case PPCISD::SUBC:
- return "PPCISD::SUBC";
- case PPCISD::SUBE:
- return "PPCISD::SUBE";
- }
- return nullptr;
-}
-
EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
EVT VT) const {
if (!VT.isVector())
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index d967018982734..680b529b4e2e5 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -34,580 +34,6 @@
namespace llvm {
- namespace PPCISD {
-
- // When adding a NEW PPCISD node please add it to the correct position in
- // the enum. The order of elements in this enum matters!
- // Values that are added between FIRST_MEMORY_OPCODE and LAST_MEMORY_OPCODE
- // are considered memory opcodes and are treated differently than other
- // entries.
- enum NodeType : unsigned {
- // Start the numbering where the builtin ops and target ops leave off.
- FIRST_NUMBER = ISD::BUILTIN_OP_END,
-
- /// FSEL - Traditional three-operand fsel node.
- ///
- FSEL,
-
- /// XSMAXC[DQ]P, XSMINC[DQ]P - C-type min/max instructions.
- XSMAXC,
- XSMINC,
-
- /// FCFID - The FCFID instruction, taking an f64 operand and producing
- /// and f64 value containing the FP representation of the integer that
- /// was temporarily in the f64 operand.
- FCFID,
-
- /// Newer FCFID[US] integer-to-floating-point conversion instructions for
- /// unsigned integers and single-precision outputs.
- FCFIDU,
- FCFIDS,
- FCFIDUS,
-
- /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
- /// operand, producing an f64 value containing the integer representation
- /// of that FP value.
- FCTIDZ,
- FCTIWZ,
-
- /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
- /// unsigned integers with round toward zero.
- FCTIDUZ,
- FCTIWUZ,
-
- /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
- /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
- VEXTS,
-
- /// Reciprocal estimate instructions (unary FP ops).
- FRE,
- FRSQRTE,
-
- /// Test instruction for software square root.
- FTSQRT,
-
- /// Square root instruction.
- FSQRT,
-
- /// VPERM - The PPC VPERM Instruction.
- ///
- VPERM,
-
- /// XXSPLT - The PPC VSX splat instructions
- ///
- XXSPLT,
-
- /// XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for
- /// converting immediate single precision numbers to double precision
- /// vector or scalar.
- XXSPLTI_SP_TO_DP,
-
- /// XXSPLTI32DX - The PPC XXSPLTI32DX instruction.
- ///
- XXSPLTI32DX,
-
- /// VECINSERT - The PPC vector insert instruction
- ///
- VECINSERT,
-
- /// VECSHL - The PPC vector shift left instruction
- ///
- VECSHL,
-
- /// XXPERMDI - The PPC XXPERMDI instruction
- ///
- XXPERMDI,
- XXPERM,
-
- /// The CMPB instruction (takes two operands of i32 or i64).
- CMPB,
-
- /// Hi/Lo - These represent the high and low 16-bit parts of a global
- /// address respectively. These nodes have two operands, the first of
- /// which must be a TargetGlobalAddress, and the second of which must be a
- /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
- /// though these are usually folded into other nodes.
- Hi,
- Lo,
-
- /// The following two target-specific nodes are used for calls through
- /// function pointers in the 64-bit SVR4 ABI.
-
- /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
- /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
- /// compute an allocation on the stack.
- DYNALLOC,
-
- /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
- /// compute an offset from native SP to the address of the most recent
- /// dynamic alloca.
- DYNAREAOFFSET,
-
- /// To avoid stack clash, allocation is performed by block and each block is
- /// probed.
- PROBED_ALLOCA,
-
- /// The result of the mflr at function entry, used for PIC code.
- GlobalBaseReg,
-
- /// These nodes represent PPC shifts.
- ///
- /// For scalar types, only the last `n + 1` bits of the shift amounts
- /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc.
- /// for exact behaviors.
- ///
- /// For vector types, only the last n bits are used. See vsld.
- SRL,
- SRA,
- SHL,
-
- /// These nodes represent PPC arithmetic operations with carry.
- ADDC,
- ADDE,
- SUBC,
- SUBE,
-
- /// FNMSUB - Negated multiply-subtract instruction.
- FNMSUB,
-
- /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign
- /// word and shift left immediate.
- EXTSWSLI,
-
- /// The combination of sra[wd]i and addze used to implemented signed
- /// integer division by a power of 2. The first operand is the dividend,
- /// and the second is the constant shift amount (representing the
- /// divisor).
- SRA_ADDZE,
-
- /// CALL - A direct function call.
- /// CALL_NOP is a call with the special NOP which follows 64-bit
- /// CALL_NOTOC the caller does not use the TOC.
- /// SVR4 calls and 32-bit/64-bit AIX calls.
- CALL,
- CALL_NOP,
- CALL_NOTOC,
-
- /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
- /// MTCTR instruction.
- MTCTR,
-
- /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
- /// BCTRL instruction.
- BCTRL,
-
- /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
- /// instruction and the TOC reload required on 64-bit ELF, 32-bit AIX
- /// and 64-bit AIX.
- BCTRL_LOAD_TOC,
-
- /// The variants that implicitly define rounding mode for calls with
- /// strictfp semantics.
- CALL_RM,
- CALL_NOP_RM,
- CALL_NOTOC_RM,
- BCTRL_RM,
- BCTRL_LOAD_TOC_RM,
-
- /// Return with a glue operand, matched by 'blr'
- RET_GLUE,
-
- /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
- /// This copies the bits corresponding to the specified CRREG into the
- /// resultant GPR. Bits corresponding to other CR regs are undefined.
- MFOCRF,
-
- /// Direct move from a VSX register to a GPR
- MFVSR,
-
- /// Direct move from a GPR to a VSX register (algebraic)
- MTVSRA,
-
- /// Direct move from a GPR to a VSX register (zero)
- MTVSRZ,
-
- /// Direct move of 2 consecutive GPR to a VSX register.
- BUILD_FP128,
-
- /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and
- /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is
- /// unsupported for this target.
- /// Merge 2 GPRs to a single SPE register.
- BUILD_SPE64,
-
- /// Extract SPE register component, second argument is high or low.
- EXTRACT_SPE,
-
- /// Extract a subvector from signed integer vector and convert to FP.
- /// It is primarily used to convert a (widened) illegal integer vector
- /// type to a legal floating point vector type.
- /// For example v2i32 -> widened to v4i32 -> v2f64
- SINT_VEC_TO_FP,
-
- /// Extract a subvector from unsigned integer vector and convert to FP.
- /// As with SINT_VEC_TO_FP, used for converting illegal types.
- UINT_VEC_TO_FP,
-
- /// PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to
- /// place the value into the least significant element of the most
- /// significant doubleword in the vector. This is not element zero for
- /// anything smaller than a doubleword on either endianness. This node has
- /// the same semantics as SCALAR_TO_VECTOR except that the value remains in
- /// the aforementioned location in the vector register.
- SCALAR_TO_VECTOR_PERMUTED,
-
- // FIXME: Remove these once the ANDI glue bug is fixed:
- /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
- /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
- /// implement truncation of i32 or i64 to i1.
- ANDI_rec_1_EQ_BIT,
- ANDI_rec_1_GT_BIT,
-
- // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
- // target (returns (Lo, Hi)). It takes a chain operand.
- READ_TIME_BASE,
-
- // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
- EH_SJLJ_SETJMP,
-
- // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
- EH_SJLJ_LONGJMP,
-
- /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
- /// instructions. For lack of better number, we use the opcode number
- /// encoding for the OPC field to identify the compare. For example, 838
- /// is VCMPGTSH.
- VCMP,
-
- /// RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the
- /// altivec VCMP*_rec instructions. For lack of better number, we use the
- /// opcode number encoding for the OPC field to identify the compare. For
- /// example, 838 is VCMPGTSH.
- VCMP_rec,
-
- /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
- /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
- /// condition register to branch on, OPC is the branch opcode to use (e.g.
- /// PPC::BLE),...
[truncated]
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/59/builds/27467 Here is the relevant piece of the build log for the reference |
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This allows SDNodes to be validated against their expected type profiles and reduces the number of changes required to add a new node. The validation functionality has detected several issues, see `PPCSelectionDAGInfo::verifyTargetNode()`. Most of the nodes have a description in `*.td` files and were successfully "imported". Those that don't have a description are listed in the enum in `PPCSelectionDAGInfo.td`. These nodes are not validated. Part of #119709. Pull Request: llvm/llvm-project#168108
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/14/builds/4696 Here is the relevant piece of the build log for the reference |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/49/builds/2570 Here is the relevant piece of the build log for the reference |
nekoshirro
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This allows SDNodes to be validated against their expected type profiles and reduces the number of changes required to add a new node. The validation functionality has detected several issues, see `PPCSelectionDAGInfo::verifyTargetNode()`. Most of the nodes have a description in `*.td` files and were successfully "imported". Those that don't have a description are listed in the enum in `PPCSelectionDAGInfo.td`. These nodes are not validated. Part of #119709. Pull Request: llvm/llvm-project#168108 Signed-off-by: Hafidz Muzakky <ais.muzakky@gmail.com>
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This allows SDNodes to be validated against their expected type profiles and reduces the number of changes required to add a new node. The validation functionality has detected several issues, see `PPCSelectionDAGInfo::verifyTargetNode()`. Most of the nodes have a description in `*.td` files and were successfully "imported". Those that don't have a description are listed in the enum in `PPCSelectionDAGInfo.td`. These nodes are not validated. Part of llvm#119709. Pull Request: llvm#168108
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This allows SDNodes to be validated against their expected type profiles and reduces the number of changes required to add a new node.
The validation functionality has detected several issues, see
PPCSelectionDAGInfo::verifyTargetNode().Most of the nodes have a description in
*.tdfiles and were successfully "imported". Those that don't have a description are listed in the enum inPPCSelectionDAGInfo.td. These nodes are not validated.Part of #119709.