[AArch64][llvm] Armv9.7-A: Add support for Virtual Memory Tagging (FEAT_MTETC) #163158

jthackray · 2025-10-13T09:38:42Z

Add the following instructions for FEAT_MTETC, which is a part of
FEAT_VMTE for Virtual Tagging:

DC ZGBVA
DC GBVA

as documented here:

jthackray · 2025-10-13T09:38:56Z

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llvmbot · 2025-10-13T09:41:06Z

@llvm/pr-subscribers-clang

@llvm/pr-subscribers-backend-aarch64

Author: Jonathan Thackray (jthackray)

Changes

Add the following instructions for FEAT_MTETC, which is a part of
FEAT_VMTE for Virtual Tagging:

DC ZGBVA
DC GBVA

as documented here:

Full diff: https://github.com/llvm/llvm-project/pull/163158.diff

8 Files Affected:

(modified) clang/test/Driver/aarch64-v97a.c (+4)
(modified) clang/test/Driver/print-supported-extensions-aarch64.c (+1)
(modified) llvm/lib/Target/AArch64/AArch64Features.td (+3)
(modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+2)
(modified) llvm/lib/Target/AArch64/AArch64SystemOperands.td (+6)
(modified) llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (+1)
(added) llvm/test/MC/AArch64/arm-mtetc.s (+29)
(modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+3-1)

diff --git a/clang/test/Driver/aarch64-v97a.c b/clang/test/Driver/aarch64-v97a.c
index 9d9e946df6f65..3c6ca22481d97 100644
--- a/clang/test/Driver/aarch64-v97a.c
+++ b/clang/test/Driver/aarch64-v97a.c
@@ -33,3 +33,7 @@
 // RUN: %clang -target aarch64 -march=armv9.7a+mpamv2 -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MPAMv2 %s
 // RUN: %clang -target aarch64 -march=armv9.7-a+mpamv2 -### -c %s 2>&1 | FileCheck -check-prefix=V97A-MPAMv2 %s
 // V97A-MPAMv2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mpamv2"
+
+// RUN: %clang -target aarch64 -march=armv9.7a+mtetc -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-MTETC %s
+// RUN: %clang -target aarch64 -march=armv9.7-a+mtetc -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-MTETC %s
+// VFAT-MTETC: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mtetc"
diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c
index 6a6f4e03e4f83..05ecc0dd8ec89 100644
--- a/clang/test/Driver/print-supported-extensions-aarch64.c
+++ b/clang/test/Driver/print-supported-extensions-aarch64.c
@@ -47,6 +47,7 @@
 // CHECK-NEXT:     mops                FEAT_MOPS                                              Enable Armv8.8-A memcpy and memset acceleration instructions
 // CHECK-NEXT:     mpamv2              FEAT_MPAMv2                                            Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions
 // CHECK-NEXT:     memtag              FEAT_MTE, FEAT_MTE2                                    Enable Memory Tagging Extension
+// CHECK-NEXT:     mtetc               FEAT_MTETC                                             Enable Virtual Memory Tagging Extension
 // CHECK-NEXT:     simd                FEAT_AdvSIMD                                           Enable Advanced SIMD instructions
 // CHECK-NEXT:     occmo               FEAT_OCCMO                                             Enable Armv9.6-A Outer cacheable cache maintenance operations
 // CHECK-NEXT:     pauth               FEAT_PAuth                                             Enable Armv8.3-A Pointer Authentication extension
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index b277d1d2e9453..d0b7ed34d0309 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -601,6 +601,9 @@ def FeatureTLBID: ExtensionWithMArch<"tlbid", "TLBID", "FEAT_TLBID",
 def FeatureMPAMv2: ExtensionWithMArch<"mpamv2", "MPAMv2", "FEAT_MPAMv2",
   "Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions">;
 
+def FeatureMTETC: ExtensionWithMArch<"mtetc", "MTETC", "FEAT_MTETC",
+  "Enable Virtual Memory Tagging Extension">;
+
 //===----------------------------------------------------------------------===//
 //  Other Features
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 107407fdc8892..eb8955111a75d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -404,6 +404,8 @@ def HasTLBID         : Predicate<"Subtarget->hasTLBID()">,
                        AssemblerPredicateWithAll<(all_of FeatureTLBID), "tlbid">;
 def HasMPAMv2        : Predicate<"Subtarget->hasMPAMv2()">,
                        AssemblerPredicateWithAll<(all_of FeatureMPAMv2), "mpamv2">;
+def HasMTETC         : Predicate<"Subtarget->hasMTETC()">,
+                       AssemblerPredicateWithAll<(all_of FeatureMTETC), "mtetc">;
 def IsLE             : Predicate<"Subtarget->isLittleEndian()">;
 def IsBE             : Predicate<"!Subtarget->isLittleEndian()">;
 def IsWindows        : Predicate<"Subtarget->isTargetWindows()">;
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index d5c95389ce868..4e81da1f6cfd2 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -205,6 +205,7 @@ def lookupDCByName : SearchIndex {
   let Key = ["Name"];
 }
 
+//                Op1    CRn     CRm     Op2
 def : DC<"ZVA",   0b011, 0b0111, 0b0100, 0b001>;
 def : DC<"IVAC",  0b000, 0b0111, 0b0110, 0b001>;
 def : DC<"ISW",   0b000, 0b0111, 0b0110, 0b010>;
@@ -241,6 +242,11 @@ def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>;
 def : DC<"GZVA",    0b011, 0b0111, 0b0100, 0b100>;
 }
 
+let Requires = [{ {AArch64::FeatureMTETC} }] in {
+def : DC<"ZGBVA",   0b011, 0b0111, 0b0100, 0b101>;
+def : DC<"GBVA",    0b011, 0b0111, 0b0100, 0b111>;
+}
+
 let Requires = [{ {AArch64::FeatureMEC} }] in {
 def : DC<"CIPAE",   0b100, 0b0111, 0b1110, 0b000>;
 def : DC<"CIGDPAE", 0b100, 0b0111, 0b1110, 0b111>;
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index b073914699d35..17f28ff2a5a7e 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3887,6 +3887,7 @@ static const struct Extension {
     {"lscp", {AArch64::FeatureLSCP}},
     {"tlbid", {AArch64::FeatureTLBID}},
     {"mpamv2", {AArch64::FeatureMPAMv2}},
+    {"mtetc", {AArch64::FeatureMTETC}},
 };
 
 static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
diff --git a/llvm/test/MC/AArch64/arm-mtetc.s b/llvm/test/MC/AArch64/arm-mtetc.s
new file mode 100644
index 0000000000000..8483e7612fc61
--- /dev/null
+++ b/llvm/test/MC/AArch64/arm-mtetc.s
@@ -0,0 +1,29 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mtetc < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+all < %s \
+// RUN:        | llvm-objdump -d --mattr=+mtetc --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+all < %s \
+// RUN:        | llvm-objdump -d --mattr=-mtetc --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mtetc < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+mtetc -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+//------------------------------------------------------------------------------
+// FEAT_MTETC Extension instructions
+//------------------------------------------------------------------------------
+
+dc zgbva, x0
+// CHECK-INST:    dc zgbva, x0
+// CHECK-ENCODING: [0xa0,0x74,0x0b,0xd5]
+// CHECK-UNKNOWN: d50b74a0 sys #3, c7, c4, #5, x0
+// CHECK-ERROR: DC ZGBVA requires: mtetc
+
+dc gbva, x0
+// CHECK-INST:    dc gbva, x0
+// CHECK-ENCODING: [0xe0,0x74,0x0b,0xd5]
+// CHECK-UNKNOWN: d50b74e0 sys #3, c7, c4, #7, x0
+// CHECK-ERROR: DC GBVA requires: mtetc
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index b489536ea5b94..fdf937fa8cfdc 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1445,7 +1445,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
       AArch64::AEK_SSVE_BITPERM, AArch64::AEK_SVESHA3,
       AArch64::AEK_SVESM4,       AArch64::AEK_CMH,
       AArch64::AEK_LSCP,         AArch64::AEK_TLBID,
-      AArch64::AEK_MPAMV2,
+      AArch64::AEK_MPAMV2,       AArch64::AEK_MTETC,
   };
 
   std::vector<StringRef> Features;
@@ -1561,6 +1561,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
   EXPECT_TRUE(llvm::is_contained(Features, "+lscp"));
   EXPECT_TRUE(llvm::is_contained(Features, "+tlbid"));
   EXPECT_TRUE(llvm::is_contained(Features, "+mpamv2"));
+  EXPECT_TRUE(llvm::is_contained(Features, "+mtetc"));
 
   // Assuming we listed every extension above, this should produce the same
   // result.
@@ -1731,6 +1732,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
       {"lscp", "nolscp", "+lscp", "-lscp"},
       {"tlbid", "notlbid", "+tlbid", "-tlbid"},
       {"mpamv2", "nompamv2", "+mpamv2", "-mpamv2"},
+      {"mtetc", "nomtetc", "+mtetc", "-mtetc"},
   };
 
   for (unsigned i = 0; i < std::size(ArchExt); i++) {

llvm/test/MC/AArch64/armv9.7a-mtetc.s

CarolineConcatto

Just needs to fix the test to replace +all. But it LGTM

llvm/test/MC/AArch64/armv9.7a-mtetc.s

jthackray · 2025-10-23T12:32:13Z

Merge activity

Oct 23, 12:32 PM UTC: A user started a stack merge that includes this pull request via Graphite.
Oct 23, 12:46 PM UTC: The Graphite merge of this pull request was cancelled.
Oct 23, 8:46 PM UTC: A user started a stack merge that includes this pull request via Graphite.
Oct 23, 10:03 PM UTC: The Graphite merge of this pull request was cancelled.

…AT_MTETC) Add the following instructions for `FEAT_MTETC`, which is a part of `FEAT_VMTE` for Virtual Tagging: * `DC ZGBVA` * `DC GBVA` as documented here: * https://developer.arm.com/documentation/ddi0602/2025-09/ * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions

…ing (FEAT_MTETC) FEAT_MTETC is now part of Armv9.7-A, so fix prefix

…ing (FEAT_MTETC) Add llvm/test/MC/AArch64/armv9.7a-mtetc-diagnostics.s

…ing (FEAT_MTETC) s/-mattr=+all/-mattr=+mtetc/ in test file

…AT_MTETC) (llvm#163158) Add the following instructions for `FEAT_MTETC`, which is a part of `FEAT_VMTE` for Virtual Tagging: * `DC ZGBVA` * `DC GBVA` as documented here: * https://developer.arm.com/documentation/ddi0602/2025-09/ * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions

jthackray requested review from CarolineConcatto, Lukacma, amilendra, kmclaughlin-arm and rgwott October 13, 2025 09:38

This was referenced Oct 13, 2025

[ARM][AArch64] Introduce the Armv9.7-A architecture version #163154

Merged

[AArch64][llvm] Armv9.7-A: Add support for FEAT_CMH and FEAT_LSCP #163155

Merged

[AArch64][llvm] Armv9.7-A: Add support for TLBI Domains (FEAT_TLBID) #163156

Merged

jthackray marked this pull request as ready for review October 13, 2025 09:40

llvmbot added clang Clang issues not falling into any other category backend:AArch64 clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' labels Oct 13, 2025

jthackray force-pushed the users/jthackray/armv9.7a-feat_mtetc branch from cef2406 to e875238 Compare October 13, 2025 16:49

jthackray mentioned this pull request Oct 15, 2025

[AArch64] (NFC) Tidy up alignment/formatting in AArch64/AArch64InstrInfo.td #163645

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CarolineConcatto reviewed Oct 16, 2025

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[AArch64][llvm] Relax mandatory features for Armv9.6-A #163973

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Base automatically changed from users/jthackray/armv9.7a-feat_mpamv2 to main October 23, 2025 22:35

jthackray added 4 commits October 23, 2025 23:35

fixup! [AArch64][llvm] Armv9.7-A: Add support for Virtual Memory Tagg…

5d91644

…ing (FEAT_MTETC) FEAT_MTETC is now part of Armv9.7-A, so fix prefix

fixup! [AArch64][llvm] Armv9.7-A: Add support for Virtual Memory Tagg…

13a389a

…ing (FEAT_MTETC) Add llvm/test/MC/AArch64/armv9.7a-mtetc-diagnostics.s

fixup! [AArch64][llvm] Armv9.7-A: Add support for Virtual Memory Tagg…

917ba9e

…ing (FEAT_MTETC) s/-mattr=+all/-mattr=+mtetc/ in test file

jthackray force-pushed the users/jthackray/armv9.7a-feat_mtetc branch from db2274f to 917ba9e Compare October 23, 2025 22:36

jthackray merged commit ca10dac into main Oct 23, 2025
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jthackray deleted the users/jthackray/armv9.7a-feat_mtetc branch October 23, 2025 22:39

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