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merged 2 commits into from
Aug 26, 2025
Merged

AMDGPU: Stop checking if registers are reserved in adjustAllocatableRegClass #155125

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c1d394e
AMDGPU: Fix not diagnosing unaligned VGPRs for vsrc operands
arsenm Aug 23, 2025
0eb1f3a
AMDGPU: Stop checking if registers are reserved in adjustAllocatableR…
arsenm Aug 24, 2025
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39 changes: 33 additions & 6 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4933,23 +4933,40 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,

int RegClass = Desc.operands()[i].RegClass;

switch (Desc.operands()[i].OperandType) {
const MCOperandInfo &OpInfo = Desc.operands()[i];
switch (OpInfo.OperandType) {
case MCOI::OPERAND_REGISTER:
if (MI.getOperand(i).isImm() || MI.getOperand(i).isGlobal()) {
ErrInfo = "Illegal immediate value for operand.";
return false;
}
break;
case AMDGPU::OPERAND_REG_IMM_INT32:
case AMDGPU::OPERAND_REG_IMM_INT64:
case AMDGPU::OPERAND_REG_IMM_INT16:
case AMDGPU::OPERAND_REG_IMM_FP32:
case AMDGPU::OPERAND_REG_IMM_V2FP32:
case AMDGPU::OPERAND_REG_IMM_BF16:
case AMDGPU::OPERAND_REG_IMM_FP16:
case AMDGPU::OPERAND_REG_IMM_FP64:
case AMDGPU::OPERAND_REG_IMM_V2FP16:
case AMDGPU::OPERAND_REG_IMM_V2INT16:
case AMDGPU::OPERAND_REG_IMM_V2INT32:
case AMDGPU::OPERAND_REG_IMM_V2BF16:
break;
case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
break;
break;
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
case AMDGPU::OPERAND_REG_INLINE_C_INT32:
case AMDGPU::OPERAND_REG_INLINE_C_FP32:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
case AMDGPU::OPERAND_REG_INLINE_C_FP32:
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
case AMDGPU::OPERAND_REG_INLINE_AC_FP64: {
Expand All @@ -4965,6 +4982,10 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
return false;
}
break;
case AMDGPU::OPERAND_INPUT_MODS:
case AMDGPU::OPERAND_SDWA_VOPC_DST:
case AMDGPU::OPERAND_KIMM16:
break;
case MCOI::OPERAND_IMMEDIATE:
case AMDGPU::OPERAND_KIMM32:
case AMDGPU::OPERAND_KIMM64:
Expand All @@ -4976,9 +4997,15 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
ErrInfo = "Expected immediate, but got non-immediate";
return false;
}
[[fallthrough]];
break;
case MCOI::OPERAND_UNKNOWN:
case MCOI::OPERAND_MEMORY:
case MCOI::OPERAND_PCREL:
break;
default:
continue;
if (OpInfo.isGenericType())
continue;
break;
}

if (!MO.isReg())
Expand Down Expand Up @@ -5915,7 +5942,7 @@ adjustAllocatableRegClass(const GCNSubtarget &ST, const SIRegisterInfo &RI,
const MachineRegisterInfo &MRI,
const MCInstrDesc &TID, unsigned RCID,
bool IsAllocatable) {
if ((IsAllocatable || !ST.hasGFX90AInsts() || !MRI.reservedRegsFrozen()) &&
if ((IsAllocatable || !ST.hasGFX90AInsts()) &&
(((TID.mayLoad() || TID.mayStore()) &&
!(TID.TSFlags & SIInstrFlags::Spill)) ||
(TID.TSFlags & (SIInstrFlags::DS | SIInstrFlags::MIMG)))) {
Expand Down
36 changes: 18 additions & 18 deletions llvm/test/CodeGen/AMDGPU/amdgpu-branch-weight-metadata.ll
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Expand Up @@ -14,9 +14,9 @@ define void @uniform_br_no_metadata(i32 noundef inreg %value, ptr addrspace(8) n
; GFX9-NEXT: s_mov_b32 s6, s19
; GFX9-NEXT: s_mov_b32 s5, s18
; GFX9-NEXT: s_mov_b32 s4, s17
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
; GFX9-NEXT: v_mov_b32_e32 v1, s16
; GFX9-NEXT: v_mov_b32_e32 v0, s21
; GFX9-NEXT: buffer_store_dword v1, v0, s[4:7], 0 offen
; GFX9-NEXT: .LBB0_2: ; %if.end
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
Expand Down Expand Up @@ -61,9 +61,9 @@ define void @uniform_br_same_weight(i32 noundef inreg %value, ptr addrspace(8) n
; GFX9-NEXT: s_mov_b32 s6, s19
; GFX9-NEXT: s_mov_b32 s5, s18
; GFX9-NEXT: s_mov_b32 s4, s17
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
; GFX9-NEXT: v_mov_b32_e32 v1, s16
; GFX9-NEXT: v_mov_b32_e32 v0, s21
; GFX9-NEXT: buffer_store_dword v1, v0, s[4:7], 0 offen
; GFX9-NEXT: .LBB1_2: ; %if.end
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
Expand Down Expand Up @@ -108,9 +108,9 @@ define void @uniform_br_then_likely(i32 noundef inreg %value, ptr addrspace(8) n
; GFX9-NEXT: s_mov_b32 s6, s19
; GFX9-NEXT: s_mov_b32 s5, s18
; GFX9-NEXT: s_mov_b32 s4, s17
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
; GFX9-NEXT: v_mov_b32_e32 v1, s16
; GFX9-NEXT: v_mov_b32_e32 v0, s21
; GFX9-NEXT: buffer_store_dword v1, v0, s[4:7], 0 offen
; GFX9-NEXT: .LBB2_2: ; %if.end
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
Expand Down Expand Up @@ -156,9 +156,9 @@ define void @divergent_br_no_metadata(i32 noundef inreg %value, ptr addrspace(8)
; GFX9-NEXT: s_mov_b32 s6, s19
; GFX9-NEXT: s_mov_b32 s5, s18
; GFX9-NEXT: s_mov_b32 s4, s17
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
; GFX9-NEXT: v_mov_b32_e32 v1, s16
; GFX9-NEXT: v_mov_b32_e32 v0, s21
; GFX9-NEXT: buffer_store_dword v1, v0, s[4:7], 0 offen
; GFX9-NEXT: .LBB3_2: ; %if.end
; GFX9-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
Expand Down Expand Up @@ -227,9 +227,9 @@ define void @divergent_br_same_weight(i32 noundef inreg %value, ptr addrspace(8)
; GFX9-NEXT: s_mov_b32 s6, s19
; GFX9-NEXT: s_mov_b32 s5, s18
; GFX9-NEXT: s_mov_b32 s4, s17
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
; GFX9-NEXT: v_mov_b32_e32 v1, s16
; GFX9-NEXT: v_mov_b32_e32 v0, s21
; GFX9-NEXT: buffer_store_dword v1, v0, s[4:7], 0 offen
; GFX9-NEXT: .LBB4_2: ; %if.end
; GFX9-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
Expand Down Expand Up @@ -297,9 +297,9 @@ define void @divergent_br_then_likely(i32 noundef inreg %value, ptr addrspace(8)
; GFX9-NEXT: s_mov_b32 s6, s19
; GFX9-NEXT: s_mov_b32 s5, s18
; GFX9-NEXT: s_mov_b32 s4, s17
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
; GFX9-NEXT: v_mov_b32_e32 v1, s16
; GFX9-NEXT: v_mov_b32_e32 v0, s21
; GFX9-NEXT: buffer_store_dword v1, v0, s[4:7], 0 offen
; GFX9-NEXT: ; %bb.2: ; %if.end
; GFX9-NEXT: s_or_b64 exec, exec, s[8:9]
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
Expand Down
11 changes: 6 additions & 5 deletions llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
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Expand Up @@ -166,13 +166,14 @@ define amdgpu_kernel void @with_private_to_flat_addrspacecast_cc_kernel(ptr addr
; GFX942-ARCH-FLAT: ; %bb.0:
; GFX942-ARCH-FLAT-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX942-ARCH-FLAT-NEXT: s_mov_b64 s[0:1], src_private_base
; GFX942-ARCH-FLAT-NEXT: v_mov_b32_e32 v2, 0
; GFX942-ARCH-FLAT-NEXT: s_mov_b32 s0, 0
; GFX942-ARCH-FLAT-NEXT: v_mov_b32_e32 v2, s0
; GFX942-ARCH-FLAT-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-ARCH-FLAT-NEXT: s_cmp_lg_u32 s2, -1
; GFX942-ARCH-FLAT-NEXT: s_cselect_b32 s0, s1, 0
; GFX942-ARCH-FLAT-NEXT: s_cselect_b32 s1, s2, 0
; GFX942-ARCH-FLAT-NEXT: v_mov_b32_e32 v0, s1
; GFX942-ARCH-FLAT-NEXT: v_mov_b32_e32 v1, s0
; GFX942-ARCH-FLAT-NEXT: s_cselect_b32 s1, s1, 0
; GFX942-ARCH-FLAT-NEXT: s_cselect_b32 s2, s2, 0
; GFX942-ARCH-FLAT-NEXT: v_mov_b32_e32 v0, s2
; GFX942-ARCH-FLAT-NEXT: v_mov_b32_e32 v1, s1
; GFX942-ARCH-FLAT-NEXT: flat_store_dword v[0:1], v2 sc0 sc1
; GFX942-ARCH-FLAT-NEXT: s_waitcnt vmcnt(0)
; GFX942-ARCH-FLAT-NEXT: s_endpgm
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
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Expand Up @@ -8,7 +8,7 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
; CHECK-NEXT: s_load_dwordx2 s[10:11], s[4:5], 0x0
; CHECK-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x10
; CHECK-NEXT: v_mov_b32_e32 v1, 0x3e21eeb6
; CHECK-NEXT: v_mov_b32_e32 v2, 0xa17f65f6
; CHECK-NEXT: v_mov_b32_e32 v20, 0
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: s_bitcmp1_b32 s0, 0
; CHECK-NEXT: s_cselect_b64 s[16:17], -1, 0
Expand All @@ -22,6 +22,7 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
; CHECK-NEXT: s_xor_b64 s[20:21], s[2:3], -1
; CHECK-NEXT: s_and_b64 s[2:3], exec, s[2:3]
; CHECK-NEXT: v_accvgpr_write_b32 a2, v0
; CHECK-NEXT: v_mov_b32_e32 v2, 0xa17f65f6
; CHECK-NEXT: v_mov_b32_e32 v3, 0xbe927e4f
; CHECK-NEXT: v_mov_b32_e32 v4, 0x19f4ec90
; CHECK-NEXT: v_mov_b32_e32 v5, 0x3efa01a0
Expand All @@ -42,7 +43,7 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
; CHECK-NEXT: v_mov_b32_e32 v18, 0x55555523
; CHECK-NEXT: v_mov_b32_e32 v19, 0xbfd55555
; CHECK-NEXT: s_and_b64 s[6:7], exec, s[18:19]
; CHECK-NEXT: v_mov_b32_e32 v20, 0
; CHECK-NEXT: v_mov_b32_e32 v21, v20
; CHECK-NEXT: ; implicit-def: $vgpr30_vgpr31
; CHECK-NEXT: ; implicit-def: $vgpr22_vgpr23
; CHECK-NEXT: s_branch .LBB0_2
Expand Down Expand Up @@ -155,7 +156,6 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
; CHECK-NEXT: s_cbranch_vccz .LBB0_1
; CHECK-NEXT: ; %bb.16: ; %._crit_edge2105.i.i.i2330
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: v_mov_b32_e32 v21, v20
; CHECK-NEXT: s_mov_b64 s[24:25], 0
; CHECK-NEXT: global_store_dwordx2 v20, v[20:21], s[12:13]
; CHECK-NEXT: s_branch .LBB0_1
Expand Down
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