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[NFC][AMDGPU] Align all gfx1250 VOP1 MC tests with downstream #149567

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Merged
merged 1 commit into from
Jul 18, 2025
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[NFC][AMDGPU] Align all gfx1250 VOP1 MC tests with downstream #149567

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39 changes: 39 additions & 0 deletions llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
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Original file line number Diff line number Diff line change
Expand Up @@ -664,6 +664,45 @@ v_cvt_f32_fp8_e32 v1, 3
v_cvt_f32_fp8_e32 v1, v3
// GFX1250: v_cvt_f32_fp8_e32 v1, v3 ; encoding: [0x03,0xd9,0x02,0x7e]

v_cvt_pk_f32_bf8_e32 v[2:3], s3
// GFX1250: v_cvt_pk_f32_bf8_e32 v[2:3], s3 ; encoding: [0x03,0xde,0x04,0x7e]

v_cvt_pk_f32_bf8_e32 v[4:5], s5
// GFX1250: v_cvt_pk_f32_bf8_e32 v[4:5], s5 ; encoding: [0x05,0xde,0x08,0x7e]

v_cvt_pk_f32_bf8_e32 v[2:3], 3
// GFX1250: v_cvt_pk_f32_bf8_e32 v[2:3], 3 ; encoding: [0x83,0xde,0x04,0x7e]

v_cvt_pk_f32_bf8_e32 v[4:5], 3
// GFX1250: v_cvt_pk_f32_bf8_e32 v[4:5], 3 ; encoding: [0x83,0xde,0x08,0x7e]

v_cvt_pk_f32_bf8_e32 v[2:3], v3
// GFX1250: v_cvt_pk_f32_bf8_e32 v[2:3], v3 ; encoding: [0x03,0xdf,0x04,0x7e]

v_cvt_pk_f32_bf8_e32 v[4:5], v3
// GFX1250: v_cvt_pk_f32_bf8_e32 v[4:5], v3 ; encoding: [0x03,0xdf,0x08,0x7e]

v_cvt_pk_f32_bf8_e32 v[4:5], v127.h
// GFX1250: v_cvt_pk_f32_bf8_e32 v[4:5], v127.h ; encoding: [0xff,0xdf,0x08,0x7e]

v_cvt_pk_f32_bf8_e32 v[4:5], v127.l
// GFX1250: v_cvt_pk_f32_bf8_e32 v[4:5], v127.l ; encoding: [0x7f,0xdf,0x08,0x7e]

v_cvt_pk_f32_fp8_e32 v[2:3], s3
// GFX1250: v_cvt_pk_f32_fp8_e32 v[2:3], s3 ; encoding: [0x03,0xdc,0x04,0x7e]

v_cvt_pk_f32_fp8_e32 v[2:3], 3
// GFX1250: v_cvt_pk_f32_fp8_e32 v[2:3], 3 ; encoding: [0x83,0xdc,0x04,0x7e]

v_cvt_pk_f32_fp8_e32 v[2:3], v3
// GFX1250: v_cvt_pk_f32_fp8_e32 v[2:3], v3 ; encoding: [0x03,0xdd,0x04,0x7e]

v_cvt_pk_f32_fp8_e32 v[4:5], v127.h
// GFX1250: v_cvt_pk_f32_fp8_e32 v[4:5], v127.h ; encoding: [0xff,0xdd,0x08,0x7e]

v_cvt_pk_f32_fp8_e32 v[4:5], v127.l
// GFX1250: v_cvt_pk_f32_fp8_e32 v[4:5], v127.l ; encoding: [0x7f,0xdd,0x08,0x7e]

v_sat_pk4_i4_i8 v1, v2
// GFX1250: v_sat_pk4_i4_i8_e32 v1, v2 ; encoding: [0x02,0xe7,0x02,0x7e]

Expand Down
3,789 changes: 3,681 additions & 108 deletions llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
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3,913 changes: 3,827 additions & 86 deletions llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
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4 changes: 0 additions & 4 deletions llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8-fake16.s
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Original file line number Diff line number Diff line change
Expand Up @@ -186,10 +186,6 @@ v_cvt_f16_bf8 v1, v2 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0]
// GFX1250: v_cvt_f16_bf8_e64_dpp v1, v2 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x10,0xf8,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05]
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU

v_cvt_f16_bf8 v150, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX1250: v_cvt_f16_bf8_e64_dpp v150, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x96,0x00,0xf8,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05]
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU

v_cvt_f16_bf8 v150, v2 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] fi:1
// GFX1250: v_cvt_f16_bf8_e64_dpp v150, v2 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x96,0x18,0xf8,0xd5,0xea,0x00,0x00,0x00,0x02,0x77,0x39,0x05]
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
Expand Down
20 changes: 8 additions & 12 deletions llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1_dpp8.s
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Expand Up @@ -202,18 +202,6 @@ v_cos_bf16_e64_dpp v5.h, v128.h dpp8:[7,6,5,4,3,2,1,0]
// GFX1250: v_cos_bf16_e64_dpp v5.h, v128.h op_sel:[1,1] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x48,0xff,0xd5,0xe9,0x00,0x00,0x00,0x80,0x77,0x39,0x05]
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU

v_cvt_f32_bf16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
// GFX1250: v_cvt_f32_bf16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xf2,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU

v_cvt_f32_bf16_e64_dpp v5, v128.h dpp8:[7,6,5,4,3,2,1,0]
// GFX1250: v_cvt_f32_bf16_e64_dpp v5, v128.h op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0xf2,0xd5,0xe9,0x00,0x00,0x00,0x80,0x77,0x39,0x05]
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU

v_cvt_f16_bf8 v150.l, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX1250: v_cvt_f16_bf8_e64_dpp v150.l, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x96,0x00,0xf8,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05]
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU

v_cvt_f16_bf8 v1.l, v2 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0]
// GFX1250: v_cvt_f16_bf8_e64_dpp v1.l, v2 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x18,0xf8,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05]
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
Expand Down Expand Up @@ -274,6 +262,14 @@ v_cvt_f16_fp8 v128.l, v2 dpp8:[7,6,5,4,3,2,1,0]
// GFX1250: v_cvt_f16_fp8_e64_dpp v128.l, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x80,0x00,0xf7,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05]
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU

v_cvt_f32_bf16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0]
// GFX1250: v_cvt_f32_bf16_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xf2,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU

v_cvt_f32_bf16_e64_dpp v5, v128.h dpp8:[7,6,5,4,3,2,1,0]
// GFX1250: v_cvt_f32_bf16_e64_dpp v5, v128.h op_sel:[1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x08,0xf2,0xd5,0xe9,0x00,0x00,0x00,0x80,0x77,0x39,0x05]
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU

v_cvt_f32_fp8 v1, v3 clamp dpp8:[7,6,5,4,3,2,1,0]
// GFX1250: v_cvt_f32_fp8_e64_dpp v1, v3 clamp dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x80,0xec,0xd5,0xe9,0x00,0x00,0x00,0x03,0x77,0x39,0x05]
// GFX12-ERR: :[[@LINE-2]]:22: error: invalid operand for instruction
Expand Down
53 changes: 49 additions & 4 deletions llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -810,6 +810,52 @@
0x03,0xd9,0x02,0x7e
# GFX1250: v_cvt_f32_fp8_e32 v1, v3 ; encoding: [0x03,0xd9,0x02,0x7e]

0x03,0xde,0x04,0x7e
# GFX1250: v_cvt_pk_f32_bf8_e32 v[2:3], s3 ; encoding: [0x03,0xde,0x04,0x7e]

0x83,0xde,0x04,0x7e
# GFX1250: v_cvt_pk_f32_bf8_e32 v[2:3], 3 ; encoding: [0x83,0xde,0x04,0x7e]

0x03,0xdf,0x04,0x7e
# GFX1250-REAL16: v_cvt_pk_f32_bf8_e32 v[2:3], v3.l ; encoding: [0x03,0xdf,0x04,0x7e]
# GFX1250-FAKE16: v_cvt_pk_f32_bf8_e32 v[2:3], v3 ; encoding: [0x03,0xdf,0x04,0x7e]

0x05,0xde,0x08,0x7e
# GFX1250: v_cvt_pk_f32_bf8_e32 v[4:5], s5 ; encoding: [0x05,0xde,0x08,0x7e]

0x83,0xde,0x08,0x7e
# GFX1250: v_cvt_pk_f32_bf8_e32 v[4:5], 3 ; encoding: [0x83,0xde,0x08,0x7e]

0x03,0xdf,0x08,0x7e
# GFX1250-REAL16: v_cvt_pk_f32_bf8_e32 v[4:5], v3.l ; encoding: [0x03,0xdf,0x08,0x7e]
# GFX1250-FAKE16: v_cvt_pk_f32_bf8_e32 v[4:5], v3 ; encoding: [0x03,0xdf,0x08,0x7e]

0xff,0xdf,0x08,0x7e
# GFX1250-REAL16: v_cvt_pk_f32_bf8_e32 v[4:5], v127.h ; encoding: [0xff,0xdf,0x08,0x7e]
# GFX1250-FAKE16: v_cvt_pk_f32_bf8_e32 v[4:5], v255/*Invalid register, operand has 'VS_32_Lo128' register class*/ ; encoding: [0xff,0xdf,0x08,0x7e]

0x7f,0xdf,0x08,0x7e
# GFX1250-REAL16: v_cvt_pk_f32_bf8_e32 v[4:5], v127.l ; encoding: [0x7f,0xdf,0x08,0x7e]
# GFX1250-FAKE16: v_cvt_pk_f32_bf8_e32 v[4:5], v127 ; encoding: [0x7f,0xdf,0x08,0x7e]

0x03,0xdc,0x04,0x7e
# GFX1250: v_cvt_pk_f32_fp8_e32 v[2:3], s3 ; encoding: [0x03,0xdc,0x04,0x7e]

0x83,0xdc,0x04,0x7e
# GFX1250: v_cvt_pk_f32_fp8_e32 v[2:3], 3 ; encoding: [0x83,0xdc,0x04,0x7e]

0x03,0xdd,0x04,0x7e
# GFX1250-REAL16: v_cvt_pk_f32_fp8_e32 v[2:3], v3.l ; encoding: [0x03,0xdd,0x04,0x7e]
# GFX1250-FAKE16: v_cvt_pk_f32_fp8_e32 v[2:3], v3 ; encoding: [0x03,0xdd,0x04,0x7e]

0xff,0xdd,0x08,0x7e
# GFX1250-REAL16: v_cvt_pk_f32_fp8_e32 v[4:5], v127.h ; encoding: [0xff,0xdd,0x08,0x7e]
# GFX1250-FAKE16: v_cvt_pk_f32_fp8_e32 v[4:5], v255/*Invalid register, operand has 'VS_32_Lo128' register class*/ ; encoding: [0xff,0xdd,0x08,0x7e]

0x7f,0xdd,0x08,0x7e
# GFX1250-REAL16: v_cvt_pk_f32_fp8_e32 v[4:5], v127.l ; encoding: [0x7f,0xdd,0x08,0x7e]
# GFX1250-FAKE16: v_cvt_pk_f32_fp8_e32 v[4:5], v127 ; encoding: [0x7f,0xdd,0x08,0x7e]

0xff,0xe6,0x02,0x7e,0x34,0x12,0x00,0x00
# GFX1250-REAL16: v_sat_pk4_i4_i8_e32 v1.l, 0x1234 ; encoding: [0xff,0xe6,0x02,0x7e,0x34,0x12,0x00,0x00]
# GFX1250-FAKE16: v_sat_pk4_i4_i8_e32 v1, 0x1234 ; encoding: [0xff,0xe6,0x02,0x7e,0x34,0x12,0x00,0x00]
Expand Down Expand Up @@ -845,9 +891,8 @@
# GFX1250-REAL16: v_sat_pk4_u4_u8_e32 v1.l, v2 ; encoding: [0x02,0xe9,0x02,0x7e]
# GFX1250-FAKE16: v_sat_pk4_u4_u8_e32 v1, v2 ; encoding: [0x02,0xe9,0x02,0x7e]

0xff,0xe8,0x02,0x7e,0x34,0x12,0x00,0x00
# GFX1250-REAL16: v_sat_pk4_u4_u8_e32 v1.l, 0x1234 ; encoding: [0xff,0xe8,0x02,0x7e,0x34,0x12,0x00,0x00]
# GFX1250-FAKE16: v_sat_pk4_u4_u8_e32 v1, 0x1234 ; encoding: [0xff,0xe8,0x02,0x7e,0x34,0x12,0x00,0x00]

0x02,0xe9,0x02,0x7f
# GFX1250-REAL16: v_sat_pk4_u4_u8_e32 v1.h, v2 ; encoding: [0x02,0xe9,0x02,0x7f]

0x02,0x93,0x02,0x7e
# GFX1250: v_permlane16_swap_b32_e32 v1, v2 ; encoding: [0x02,0x93,0x02,0x7e]
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